• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.810-813
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• 2008

본 논문에서 연구하고 구현된 JTAG(Joint Test Action Group) Writer는 하나의 SoC(System On a Chip)만 지원하도록 설계된 기존 제품의 단점을 보완할 수 있도록 각 SoC의 제조 회사에서 제공하는 BSDL(Boundary Scan Description Language)을 이용하여 여러 가지 SoC에 쉽게 사용할 수 있도록 모듈화 했다. 그리고 기존 제품들이 사용하고 있는 직렬 포트나 병렬 포트 대신 안정적이고 편리한 USB(Universal Serial Bus) 접속규격을 지원하도록 개선했다.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.472-474
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• 2005

In WDM/SCM-PON system more than thousand signals must be gathered to monitor for operation. We have implemented IEEE STD 1149.1 JTAG serial interface bus to gather and monitor analog signals. Required area is just $5{\times}5mm^2$. Gathering time per one signal is $1.75{\mu}$ second. Performance to gather is better than that defined in SFF-8472.

• Korea Multimedia Society
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• v.7 no.3
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• pp.1-11
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• 2003

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.41-46
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• 2008

Since embedded software is sensitive to the resources and environment of target system, it should be debugged in the same environment as actual target system. However, existing tools to debug embedded software, in which access to internal signal or resources is limited, are uneconomical. In the thesis, economical and practical JTAG Adapter that can use open GDB is suggested. It can remove existing limitations of environment implementation that have many difficulties in implementing an environment for remote debugging. Hence, the thesis provides economical interfacing environment that can debug ubiquitous embedded software inside remote system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.66-72
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• 2002

In this paper, we implemented the GenJTAG, a CAD tool, which generates a code of boundary scan circuit supporing a board level testing and d BIST(Built-In Self Test) written in verilog-HDL. A boundary scan circuit code that supports user's own BIST instructions is generated based on the informations from the users. Most CAD tools hardly allow users to add their own BIST instructions because the generated code described in gate-level. But the GenJTAG generates a behavioral boundary scan circuit code so users can easily make a change on the generated code.

• Journal of Platform Technology
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• v.10 no.4
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• pp.62-69
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• 2022

Flight control systems installed on unmanned aircraft require thorough verification from the design stage. This verification is made through the integrated flight control test environment. Typically, a debugger is used to monitor the internal state of a flight control computer in real time. Emulator with a real-time memory monitor and trace is relatively expensive. The JTAG Emulator is unable to operate in real time and has limitations that cannot be caught up with the processing speed of latest high-speed processors. In this paper, we describe the results of the development of internal monitoring software for drone flight control computer processors based on NUTTX/PIXHAWK. The results of this study show that the functions provided compared to commercial debugger are limited, but it can be sufficiently used to verify the flight control system using this system under limited budget.

• Journal of information and communication convergence engineering
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• v.3 no.2
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• pp.96-100
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• 2005

Since ubiquitous embedded software is sensitive to the resources and environment of target system, it should be debugged in the same environment as actual target system. However, existing tools to debug embedded software, in which access to internal signal or resources is limited, are uneconomical. In the thesis, economical and practical USB-JTAG Adapter that can use open GDB is suggested. It can remove existing limitations of environment implementation that have many difficulties in implementing an environment for remote debugging. Hence, the thesis provides economical interfacing environment that can debug ubiquitous embedded software inside remote system.

• Proceedings of the Korean Society of Computer Information Conference
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• 2011.06a
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• pp.149-153
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• 2011

2010년에는 국내에 Smart Phone이 확산되면서, Smart Phone은 단순한 음성통신정보 전달 이외에 기존의 인터넷 PC가 정보를 전달 할 수 있는 전자책, 영화, 음악, 콘텐츠 영역으로 확장되고 있다. 하지만 Smart Phone 사용자들은 멀티미디어 저작권 콘텐츠를 불법으로 이용하고 있다. 또한 이동통신 단말로서 Smart Phone관련 범죄 증거의 생성, 저장된 디지털 증거는 증거의 활용도가 높아 모바일 포렌식 연구가 필요하다. 본 논문에서 Smart Phone에서 저작권 위반 내용들을 전자책, 영화, 음악, 콘텐츠 영역으로 조사한다. 저작권 위반 Smart Phone 증거자료를 추출하고 분석하기 위한 SYN 방식과 JTAG 방식을 연구한다. Smart Phone SYN 방식과 JTAG 방식으로 Smart Phone의 저작권 위반 자료를 추출하여 복원하고, 자료를 분석하였다. 본 연구 결과는 저작권위반 단속 기술 향상과 포렌식 수사 기술 발전에 기여 할 수 있을 것이다.

• The KIPS Transactions:PartA
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• v.12A no.7 s.97
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• pp.583-588
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• 2005

To develop SoC program for embedded systems, a tool that can remotely debug from host system is needed. Because the existing remote debugging systems using GDB don't offer information of the SoC program execution in real-time, it is difficult to observe condition of the program execution, and also they have limited characteristics to tools and use costly adaptors. In this paper, a real-time tracking tool that can record SoC status on the nv each execution of the assigned instructions is introduced and an economical USB-JTAG adaptor is proposed. And it is shown that this tool can track the execution of a composed program in the target system based on PXA255 processor.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.5
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• pp.980-986
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• 2007

Boundary scan test structure(JTAG IEEE 1149.1 standard) that supports an internal scan chain is generally being used to test CUT(circuit under test). Since the internal scan chain can only have a single scan-in port and a single scan-out port; however, existing boundary test methods can not be used when multiple scan chains are present in CUT. Those chains must be stitched to form a single scan chain as shown in this paper. We propose an efficient boundary scan test structure that adds a circuit called Clock Group Register(CGR) for multiple clocks testing within the design of multiple scan chains. The proposed CGR has the function of grouping clocks. By adding CGR to a previously existing boundary scan design, the design is modified. This revised scan design overcomes the limitation of supporting a single scan-in port and out port, and it bolsters multiple scan-in ports and out ports. Through our experiments, the effectiveness of CGR is proved. With this, it is possible to test more complicated designs that have high density with a little effort. Furthermore, it will also benefit in designing those complicated circuits.