• ETRI Journal
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• v.28 no.4
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• pp.453-460
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• 2006

In this article, we introduce a new class of product codes based on convolutional codes, called convolutional product codes. The structure of product codes enables parallel decoding, which can significantly increase decoder speed in practice. The use of convolutional codes in a product code setting makes it possible to use the vast knowledge base for convolutional codes as well as their flexibility in fast parallel decoders. Just as in turbo codes, interleaving turns out to be critical for the performance of convolutional product codes. The practical decoding advantages over serially-concatenated convolutional codes are emphasized.

• Journal of Communications and Networks
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• v.15 no.4
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• pp.411-421
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• 2013

Digital fountain codes are record-breaking codes for erasure channels. They have many potential applications in both wired and wireless communications. Most existing digital fountain codes operate over binary fields using an iterative belief-propagation (BP) decoding algorithm. In this paper, we propose a new iterative decoding algorithm for both binary and nonbinary fields. The basic form of our proposed algorithm considers both degree-1 and degree-2 check nodes (instead of only degree-1 check nodes as in the original BP decoding scheme), and has linear complexity. Extensive simulation demonstrates that it outperforms the original BP decoding scheme, especially for a small number of source packets. The enhanced form of the proposed algorithm combines the basic form of the algorithm and a guess-based algorithm to further improve the decoding performance. Simulation results demonstrate that it can provide better decoding performance than the guess-based algorithm with fewer guesses, and can achieve decoding performance close to that of the maximum likelihood decoder at a much lower decoding complexity. Last, we show that our nonbinary scheme has the potential to outperform the binary scheme when choosing suitable degree distributions, and furthermore it is insensitive to the size of the Galois field.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.175-178
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• 1998

In this paper, turbo codes with the DC-free trellis codes based on partition chain as constituent codes are presente. And efficient methods to design the DC-free turbo codes are introduced. An iterative decoding with the MAP algorithm is used for the decoding of the turbo codes designed by various methods. As results of simulations, the presented DC-free turbo codes show better error performances than the DC-free trellis codes.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.11
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• pp.36-42
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• 2010

This paper presents a hybrid approach to the construction of quasi-cyclic (QC) low-density parity-check (LDPC) codes based on parallel bundles in Euclidean geometries and circulant permutation matrices. Codes constructed by this method are shown to be regular with large girth and low density. Simulation results show that these codes perform very well with iterative decoding and achieve reasonably large coding gains over uncoded system.

• Journal of Communications and Networks
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• v.17 no.3
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• pp.213-220
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• 2015

In this paper, we present a reliability-based iterative proportionality-logic decoding algorithm for two classes of structured low-density parity-check (LDPC) codes. The main contributions of this paper include: 1) Syndrome messages instead of extrinsic messages are processed and exchanged between variable nodes and check nodes, which can reduce the decoding complexity; 2) a more flexible decision mechanism is developed in which the decision threshold can be self-adjusted during the iterative process. Such decision mechanism is particularly effective for decoding the majority-logic decodable codes; 3) only part of the variable nodes satisfying the pre-designed criterion are involved for the presented algorithm, which is in the proportionality-logic sense and can further reduce the computational complexity. Simulation results show that, when combined with factor correction techniques and appropriate proportionality parameter, the presented algorithm performs well and can achieve fast decoding convergence rate while maintaining relative low decoding complexity, especially for small quantized levels (3-4 bits). The presented algorithm provides a candidate for those application scenarios where the memory load and the energy consumption are extremely constrained.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.12
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• pp.5401-5421
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• 2016

Both low-density parity-check (LDPC) codes and the multiple access technique of spatially coupling data transmission (SCDT) can be expressed in bipartite graphs. To improve the performance of iterative demodulation and decoding for SCDT, a novel joint sparse graph (JSG) with SCDT and LDPC codes is constructed. Based on the JSG, an approach for iterative joint demodulation and decoding by belief propagation (BP) is presented as an exploration of the flooding schedule, and based on BP, density evolution equations are derived to analyze the performance of the iterative receiver. To accelerate the convergence speed and reduce the complexity of joint demodulation and decoding, a novel serial schedule is proposed. Numerical results show that the joint demodulation and decoding for SCDT based on JSG can significantly improve the system's performance, while roughly half of the iterations can be saved by using the proposed serial schedule.

• Journal of Satellite, Information and Communications
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• v.10 no.3
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• pp.73-77
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• 2015

In this paper, we present two simulation methods to investigate the effect of excluding bit errors on generating the extrinsic information transfer (EXIT) chart for low density parity check (LDPC) and turbo codes. We utilized the simulation methods including and excluding bit errors to generate EXIT chart which was originally proposed for turbo codes. The generated EXIT charts for LDPC and turbo codes shows that the presented methods appropriately demonstrates the performance behaviours of iterative decoding for LDPC and turbo codes. Analysis on the simulation results demonstrates that the EXIT chart excluding the bit errors shows only a small part of the curves where the amount of information is too large.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1143-1149
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• 2006

In this paper, the modified iterative decoding algorithm[8] by partitioning check nodes is applied to low-density parity-check(LDPC) codes in IEEE 802.16e standards, which gives us the improvement for convergence speed of decoding. Also, the new method of check node partitioning which is suitable for decoding of the LDPC codes in IEEE 802.16e system is proposed. The improvement of convergence speed in decoding reduces the number of iterations and thus the computational complexity of the decoder. The decoding method by partitioning check nodes can be applied to the LDPC codes whose decoder cannot be implemented in the fully parallel processing as an efficient sequential processing method. The modified iterative decoding method of LDPC codes using the proposed check node partitioning method can be used to implement the practical decoder in the wireless communication systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7C
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• pp.611-617
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• 2010

In this paper, we investigate the performances of the serial concatenated convolutional codes (SCCC) and low-density parity-check (LDPC) codes on perpendicular magnetic recording (PMR) channels. We discuss the performance of two systems when user bit-densities are 1.7, 2.0, 2.4 and 2.8, respectively. The SCCC system is less complex than LDPC system. The SCCC system consists of recursive systematic convolutional (RSC) codes encoder/decoder, precoder and random interleaver. The decoding algorithm of the SCCC system is the soft message-passing algorithm and the decoding algorithm of the LDPC system is the log domain sum-product algorithm (SPA). When we apply the iterative decoding between channel detector and the error control codes (ECC) decoder, the SCCC system is compatible with the LDPC system even at the high user bit density.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.28-31
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• 2003

In this paper, it proposes the efficient iterative decoding stop criterion using the variance value of LLR. It is verifying that the proposal iterative de-coding stop criterion can be reduced the average iterative decoding number. The proposal algorithm md hardware synthesize to use the Synopsys Tool, performance validations perform through the ModelSim.