• Title/Summary/Keyword: Iteration scheme

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A NEW ITERATION METHOD FOR FIXED POINT OF NONEXPANSIVE MAPPING IN UNIFORMLY CONVEX BANACH SPACE

  • Omprakash, Sahu;Amitabh, Banerjee;Niyati, Gurudwan
    • Korean Journal of Mathematics
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    • v.30 no.4
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    • pp.665-678
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    • 2022
  • The aim of this paper is to introduce a new iterative process and show that our iteration scheme is faster than other existing iteration schemes with the help of numerical examples. Next, we have established convergence and stability results for the approximation of fixed points of the contractive-like mapping in the framework of uniformly convex Banach space. In addition, we have established some convergence results for the approximation of the fixed points of a nonexpansive mapping.

A New Shape Adaptation Scheme to Affine Invariant Detector

  • Liu, Congxin;Yang, Jie;Zhou, Yue;Feng, Deying
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.4 no.6
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    • pp.1253-1272
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    • 2010
  • In this paper, we propose a new affine shape adaptation scheme for the affine invariant feature detector, in which the convergence stability is still an opening problem. This paper examines the relation between the integration scale matrix of next iteration and the current second moment matrix and finds that the convergence stability of the method can be improved by adjusting the relation between the two matrices instead of keeping them always proportional as proposed by previous methods. By estimating and updating the shape of the integration kernel and differentiation kernel in each iteration based on the anisotropy of the current second moment matrix, we propose a coarse-to-fine affine shape adaptation scheme which is able to adjust the pace of convergence and enable the process to converge smoothly. The feature matching experiments demonstrate that the proposed approach obtains an improvement in convergence ratio and repeatability compared with the current schemes with relatively fixed integration kernel.

Improvement of the Adaptive Modulation System with Optimal Turbo Coded V-BLAST Technique using STD Scheme (선택적 전송 다이버시티 기법을 적용한 최적의 터보 부호화된 V-BLAST 적응변조 시스템의 성능 개선)

  • Ryoo, Sang-Jin;Choi, Kwang-Wook;Lee, Kyung-Hwan;You, Cheol- Woo;Hong, Dae-Ki;Hwang, In-Tae;Kim, Cheol-Sung
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.2
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    • pp.6-14
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    • 2007
  • In this paper, we propose and observe the Adaptive Modulation system with optimal Turbo Coded V-BLAST (Vertical-Bell-lab Layered Space-Time) technique that is applied the extrinsic information from MAP (Maximum A Posteriori) Decoder in decoding Algorithm of V-BLAST: ordering and slicing. The extrinsic information is used by a priori probability and the system decoding process is composed of the Main Iteration and the Sub Iteration. And comparing the proposed system with the Adaptive Modulation system using conventional Turbo Coded V-BLAST technique that is simply combined V-BLAST with Turbo Coding scheme, we observe how much throughput performance has been improved. In addition, we observe the proposed system using STD (Selection Transmit Diversity) scheme. As a result of simulation, Comparing with the conventional Turbo Coded V-BLAST technique with the Adaptive Modulation systems, the optimal Turbo Coded V-BLAST technique with the Adaptive Modulation systems has better throughput gain that is about 350 Kbps in 11 dB SNR range. Especially, comparing with the conventional Turbo Coded V-BLAST technique using 2 transmit and 2 receive antennas, the proposed system with STD (Selection Transmit Diversity) scheme show that the improvement of maximum throughput is about 1.77 Mbps in the same SNR range.

Design of Asynchronous 16-Bit Divider Using NST Algorithm (NST알고리즘을 이용한 비동기식 16비트 제산기 설계)

  • 이우석;박석재;최호용
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.3
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    • pp.33-42
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    • 2003
  • This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

A NEW METHOD FOR A FINITE FAMILY OF PSEUDOCONTRACTIONS AND EQUILIBRIUM PROBLEMS

  • Anh, P.N.;Son, D.X.
    • Journal of applied mathematics & informatics
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    • v.29 no.5_6
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    • pp.1179-1191
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    • 2011
  • In this paper, we introduce a new iterative scheme for finding a common element of the set of fixed points of a finite family of strict pseudocontractions and the solution set of pseudomonotone and Lipschitz-type continuous equilibrium problems. The scheme is based on the idea of extragradient methods and fixed point iteration methods. We show that the iterative sequences generated by this algorithm converge strongly to the common element in a real Hilbert space.

A general dynamic iterative learning control scheme with high-gain feedback

  • Kuc, Tae-Yong;Nam, Kwanghee
    • 제어로봇시스템학회:학술대회논문집
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    • 1989.10a
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    • pp.1140-1145
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    • 1989
  • A general dynamic iterative learning control scheme is proposed for a class of nonlinear systems. Relying on stabilizing high-gain feedback loop, it is possible to show the existence of Cauchy sequence of feedforward control input error with iteration numbers, which results in a uniform convergance of system state trajectory to the desired one.

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THREE-STEP MEAN VALUE ITERATIVE SCHEME FOR VARIATIONAL INCLUSIONS AND NONEXPANSIVE MAPPINGS

  • Zhang, Fang;Su, Yongfu
    • Journal of applied mathematics & informatics
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    • v.27 no.3_4
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    • pp.557-566
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    • 2009
  • In this paper, we present the three-step mean value iterative scheme and prove that the iteration sequence converge strongly to a common element of the set of fixed points of a nonexpansive mappings and the set of the solutions of the variational inclusions under some mild conditions. The results presented in this paper extend, generalize and improve the results of Noor and Huang and some others.

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FUZZY SLIDING MODE ITERATIVE LEARNING CONTROL Of A MANIPULATOR

  • Park, Jae-Sam
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1483-1486
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    • 2002
  • In this paper, a new scheme of iterative loaming control of a robot manipulator is presented. The proposed method uses a fuzzy sliding mode controller(FSMC), which is designed based on the similarity between the fuzzy logic control(FLC) and the sliding mode control(SMC), for the feedback. With this, the proposed method makes possible fDr fast iteration and has advantages that no linear approximation is used for the derivation of the learning law or in the stability proof Full proof of the convergence of the fuzzy sliding base learning scheme Is given.

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An FPGA Design of High-Speed Turbo Decoder

  • Jung Ji-Won;Jung Jin-Hee;Choi Duk-Gun;Lee In-Ki
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.6C
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    • pp.450-456
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    • 2005
  • In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top, and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.

Parameter learning of algebraic systems

  • Kuc, Tae-yong;Lee, Jin-Soo
    • 제어로봇시스템학회:학술대회논문집
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    • 1991.10b
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    • pp.1864-1866
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    • 1991
  • We present a parameter estimator which operates in the domain of iteration sequence. The scheme can be applied to identify unknown algebraic system whose uncertainty is parametric.

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