• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.421-424
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• 2004

As the deep sub-micron devices are recently integrated high package density, novel process method for sub $0.1{\mu}m$ devices is required to get the superior thin gate oxide characteristics and reliability. However, few have reported on the electrical quality and reliability on the thin gate oxide. In this paper I will recommand a novel shallow trench isolation structure for thin gate oxide $30{\AA}$ of deep sub-micron devices. Different from using normal LOCOS technology, novel shallow trench isolation have a unique 'inverse narrow channel effects' when the channel width of the devices is scaled down shallow trench isolation has less encroachment into the active device area. Based on the research, I could confirm the successful fabrication of shallow trench isolation(STI) structure by the SEM, in addition to thermally stable silicide process was achiever. I also obtained the decrease threshold voltage value of the channel edge and the contact resistance of $13.2[\Omega/cont.]$ at $0.3{\times}0.3{\mu}m^2$. The reliability was measured from dielectric breakdown time, shallow trench isolation structure had tile stable value of $25[%]{\sim}90[%]$ more than 55[sec].

• 한국지진공학회논문집
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• 제8권2호
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• pp.9-17
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• 2004

기존 교량 중 내진 설계가 되어 있지 않은 교량의 내진 성능에 관한 평가는 향후 발생 가능한 지진에 대한 대비로써 중요하다. 성능평가 결과, 소요의 내진 성능을 보유하고 있지 못하다면 그에 대한 보강이 필요하며 보강방법으로는 여러 가지가 있다. 그 중 지진격리증기를 이용한 내진 보강은 교량에서 교각이나 기초 등에 추가적인 시공 없이 기존 받침을 교체함으로써 비교적 간단하게 수행할 수 있다. 본 논문에서는 최근 그 시공사례가 증가하고있는 지진격리증기를 기존 비내진 교량의 보강에 사용할 때 교량의 내진 성능향상을 합리적으로 규명하기 위해 기존상태의 교량 및 지진격리장치로서 내진 보강된 교량의 내진 성능을 비교하였다. 이를 위해 기존 교량 및 내진 보강된 교량에 대해 비선형 정적ㆍ동적 해석을 수행하였으며 목표 수준의 지진에 대하여 각각의 응답을 산정하고 이를 비교하여 내진 성능 향상을 확인하였다.

• Structural Monitoring and Maintenance
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• 제10권3호
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• pp.243-260
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• 2023

Indonesia has had seismic codes for earthquake-resistant structures designs since 1970 and has been updated five times to the latest in 2019. In updating the Indonesian seismic codes, seismic hazard maps for design also update, and there are changes to the Peak Ground Acceleration (PGA). Indonesian seismic design uses the concept of building performance levels consisting of Immediate occupancy (IO), Life Safety (LS), and Collapse Prevention (CP). Related to this performance level, cases still found that buildings were damaged more than their performance targets after the earthquake. Based on the above issues, this study aims to analyze the performance of base isolation design on existing target buildings and analyze the seismic fragility for a case study in Indonesia. The target building is a prototype design 8-story medium-rise residential building using the reinforced concrete moment frame structure. Seismic fragility analysis uses Incremental Dynamic Analysis (IDA) with Nonlinear Time History Analysis (NLTHA) and eleven selected ground motions based on soil classification, magnitude, fault distance, and earthquake source mechanism. The comparison result of IDA shows a trend of significant performance improvement, with the same performance level target and risk category, the base isolation structure can be used at 1.46-3.20 times higher PGA than the fixed base structure. Then the fragility analysis results show that the fixed base structure has a safety margin of 30% and a base isolation structure of 62.5% from the PGA design. This result is useful for assessing existing buildings or considering a new building's performance.

• Journal of Power Electronics
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• 제8권1호
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• pp.51-59
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• 2008

This paper addresses several issues concerning the analysis, design, modeling, simulation and development of single-phase, single-switch, power factor corrected AC-DC high frequency switching converter topologies with transformer isolation. A detailed analysis and design is presented for single-switch topologies, namely forward buck, flyback, Cuk, Sepic and Zeta buck-boost converters, with high frequency isolation for discontinuous conduction modes (DCM) of operation. With an awareness of modem design trends towards improved performance, these switching converters are designed for low power rating and low output voltage, typically 20.25W with 13.5V in DCM operation. Laboratory prototypes of the proposed single-switch converters in DCM operation are developed and test results are presented to validate the proposed design and developed model of the system.

• 대한전자공학회논문지TC
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• 제41권6호
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• pp.87-92
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• 2004

슬롯결합형 마이크로스트립 방향성결합기의 반사계수와 분리도를 동시에 개선시키기 위하여 기존의 사각형 형태의 슬롯에 주기적으로 다수의 슬롯이 추가되었다. 방향성결합기의 2 개모드간 위상속도와 등가회로를 이용하여 설계 방정식을 도출하였다. 이상적인 성능이 설계 예제를 통하여 가능함을 확인하였다.

• 오토저널
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• 제12권4호
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• pp.47-55
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• 1990

This study is the first step for the grasp of transfer path to the vibration generated from the automotive engine and consideration of counterplan for optimal design and low vibration, low noise of the exhaust system. In this study, by applying the theory of modal analysis and experiment, vibrational reduction effect is evaluated according to the attachment of flexible coupling to the exhaust system. And data for the design is suggested to improve the characteristics of vibration. The vibration isolation and damping characteristics are improved due to the attachment of flexible coupling to the exhaust system. As a result, it is identified that flexible coupling which has good flexibility is more effective for the improvement of vibrational characteristics. By the estimation of modeshape of vibration, the location of optimal damping hanger is determined in the viewpoint of vibration isolation. Also it is confirmed that the characteristics of vibration is improved due to the attachment of damping hanger.

• Journal of electromagnetic engineering and science
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• 제13권4호
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• pp.263-266
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• 2013

A novel compact and low-loss VHF bandpass filter is presented with enhanced stopband performance using metamaterial zeroth order resonator (ZOR) characteristics. An in-line ZOR filter is initially suggested and changed to have transmission zeros (TZs) due to source-load coupling for effective improvement of the isolation from UHF wireless channels. The proposed filter is smaller than 1/10 of the conventional filters in terms of size and has relatively very low insertion loss (< 1 dB for the electromagnetic (EM) simulation and < 3 dB for the measurement) and return loss (<-20 dB) in the passband due to the approximately 80% size reduction and the higher isolation in the stopband due to the TZs. The circuit and EM simulation are in good agreement with the measurements.

• 한국공간구조학회논문집
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• 제8권5호
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• pp.75-82
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• 2008

본 연구에서는 최상층면진시스템을 적용한 고층건물의 진동제어 가능성을 검토하여 보았다. 이를 위하여 20층 및 50층 건물을 예제구조물로 선택하였고 El Centro 남북방향 성분을 지진하중으로 사용하여 수치해석을 수행하였다. 그리고 인공풍하중을 사용하여 풍하중에 대한 예제구조물의 사용성을 검토하였다. 면진되는 상부층의 수를 변화시켜가면서 구조물의 응답을 평가함으로써 최적의 면진질량에 대해서 검토하였다. 또한 상부층면진시스템의 고유진동주기 변화에 따른 진동제어성능의 변화를 고정기초구조물과 비교하여 검토하였다. 해석결과 최상층면진시스템은 동조질량감쇠기로서 활용될 수 있으며 풍하중 및 지진하중에 대한 고층건물의 동적응답을 효과적으로 저감시킬 수 있었다.

• 한국지진공학회논문집
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• 제11권6호
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• pp.69-78
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• 2007

본 연구에서는 원자력발전소 비상디젤발전기의 내진안전성을 정량적으로 평가하기 위하여 지진취약도 분석방법을 제안하고 제안한 방법을 이용하여 비상디젤발전기의 지진취약도를 평가하여 정량적인 지진위험도를 제시하였다. 기존의 비상디젤발전기뿐만 아니라 면진장치를 설치하여 지진력 저감효과를 증대시킨 비상디젤발전기에 대한 지진취약도 분석을 함께 수행하여 비상디젤발전기와 같은 대형 회전기기의 경우 면진장치를 통한 지진취약도의 변화를 살펴보았다. 최종적으로 지진취약도 결과를 이용하여 HCLPF값의 변화를 비교하여 면진에 의하여 비상디젤발전기의 취약도를 크게 개선 할 수 있는 것을 알 수 있었으며, 면진된 경우 면진장치의 파괴가 전체 거동을 지배하므로 면진장치의 성능개선이 필요한 것을 알 수 있었다.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.