• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.212-215
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• 1999

High-speed device is essential to optoelectric IC for optical storage system such as CD-ROM, DVD, and to ADC for high-speed communication system. This paper represents the BiCMOS process which contains high-speed SAVEN bipolar transistor and analyzes the frequency and switching characteristics of it briefly. Finally, to prove that the SAVEN device is adequate for high-speed system, latched comparator operating at 500MHz is designed with the SPICE parameter extracted from BiCMOS device simulation.

• 전자공학회논문지A
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• 제32A권12호
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• pp.209-219
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• 1995

As a new algorithm for RC tree delay estimation, we propose a $\tau$-model of the driver and a moment propagation method. The $\tau$-model represents the driver as a Thevenin equivalent circuit which has a one-time-constant voltage source and a linear resistor. The new driver model estimates the input voltage waveform applied to the RC more accurately than the k-factor model or the 2-piece waveform model. Compared with Elmore method, which is a lst-order approximation, the moment propagation method, which uses $\pi$-model loads to calculate the moments of the voltage waveform on each node of RC trees, gives more accurate results by performing higher-order approximations with the same simple tree walking algorithm. In addition, for the instability problem which is common to all the approximation methods using the moment matching technique, we propose a heuristic method which guarantees a stable and accureate 2nd order approximation. The proposed driver model and the moment propagation method give an accureacy close to SPICE results and more than 1000 times speedup over circuit level simulations for RC trees and FPGA interconnects in which the interconnect delay is dominant.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 하계학술대회 논문집
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• pp.525-528
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• 1990

In this paper, a CMOS Operational Transconductance Amplifier (OTA) which is used for high-frequency operation has been designed and simulated by SPICE 2G program. To increase input linear range, the input stage is designed by cross-coupled pair. And the output stage insert buffer stage for the buffing and gain. The band-width of designed OTA is $50{\sim}60$ [MHz].

• 대한전자공학회논문지
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• 제22권5호
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• pp.50-56
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• 1985

A common failure mechanism in bulk CMOS integrated circuits is the latch-up of parasitic SCR structure inherent in the bulk CMOS structure. Latch-up triggering and holding charac-teristics have been measured in the test devicrs which include conventional and Schottky-damped CMOS structures with various well depths and n+/p+ spacings. It is demonstrated that Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS. Finally, the simulation results by circuit simulation program (SPICE) are compared with measured results in order to verify the validity of the latch-up modal composed of nan, pnp transistors and two external resistors.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2009년도 춘계학술대회 논문집
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• pp.1943-1950
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• 2009

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.

• 전자공학회논문지B
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• 제28B권11호
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• pp.859-865
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• 1991

The paper proposes a design of high-speed dynamic CMOS PLA (Programmable Logic Array) which performs stable circuit operation. The race problem which nay occur in a NOR-NOR implementation of PLA is free in the proposed dynamic CMOS PLA by delaying time between the clocks to the AND- and to the OR-planes. The delay element has the same structure as the product line of the longest delay in the AND p`ane. Therefore it is unnecessary to design the delay element or to calculate correct delay time. The correct delay generated by the delay element makes the dynamic CMOS PLA to perform correct and stable circuit operation. Theproposed dynamic CMOS PLA has few variation of switching delay with the increasing number of inputs or outputs in PLA. It is verified by SPICE circuit simulation that the proposed dynamic CMOS PLA has the better performance over existing dynamic CMOS PLA's.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.167-170
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• 2000

This paper describes a novel multi-operand radix-2 signed-digit(SD) adder. The novel multi-operand addition algorithm can eliminate carry propagation chain by dividing the input operands into even place part and odd place part, and adding them each. The multi-operand adder with this algorithm can add six operands in parallel, and is faster than the ordinary method of SD adder binary tree. A hardware model for proposed adder is shown which is implemented by the current-mode MOSFET circuit technology. Simulations have been made by SPICE in order to verify the function of the proposed circuit.

• Transactions on Electrical and Electronic Materials
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• 제5권6호
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• pp.237-240
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• 2004

In this paper, a CMOS bridge rectifier for HF and microwave RFID systems is presented. The proposed RFID CMOS bridge rectifier is designed with two NMOSs and two PMOSs whose gates are connected to the antenna, and it is operated as a full wave bridge rectifier. The simulation results obtained with SPICE show the well rectified and high enough DC output voltages for the operating frequencies of 13.56 MHz, 915 MHz, and 2.45 GHz which are used in various RFID systems. The obtained DC output voltages are sufficiently high for driving the low power microchip in RFID transponder for the frequency range of HF and microwave.

• 전자공학회논문지B
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• 제32B권11호
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.335-336
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• 2007

A new current-programmed pixel circuit for activematrix organic light emitting diodes (AMOLEDs), based on Organic TFTs (OTFTs), is proposed and verified by SPICE simulations. The simulation results show that the proposed pixel circuit, which is a current mirror structure consisting of five Organic TFTs and one capacitor, has reliable linear characteristics between input current and output OLED current. Also, the threshold voltage degradation of Organic TFTs due to long time operation stress is well compensated to reliable values.