• Journal of Advanced Navigation Technology
• /
• v.14 no.3
• /
• pp.446-451
• /
• 2010

This paper addressed an another scheme of distortion estimation method based on simplified inverse quantization in H.264/AVC. The distortion is calculated by the difference of coefficient between quantized transform coefficients and that of inverse. In general, these process included such transforms as discrete cosine transform(DCT), quantization, inverse quantization(IQ), and Inverse DCT(IDCT). In proposed approach, IQ as well as IDCT process are skipped because of replacing a couple of approximated formulas. Some simulation have been conducted and it showed that the PSNR was almost the same, and reduced the rate-distortion optimization(RDO) mode decision time of 8~15% in comparison with conventional method.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.4
• /
• pp.106-114
• /
• 2016

In this paper, we propose an efficient integer inverse transform structure for vp9 decoder. The proposed structure is a hardware structure which is easy to control and requires less hardware resources, and shares algorithms for realizing entire DCT(Discrete Cosine Transform), ADST(Asymmetric Discrete Sine Transform) and WHT(Walsh-Hadamard Transform) in vp9. The integer inverse transform for vp9 google model has a fast structure, named butterfly structure. The integer inverse transform for google C model, unlike universal fast structure, takes a constant rounding shift operator on each stage and includes an asymmetrical sine transform structure. Thus, the proposed structure approximates matrix coefficient values for all transform mode and is used to matrix operation method. With the proposed structure, shared operations for all inverse transform algorithm modes can be possible with reduced number of multipliers compared to the butterfly structure, which in turn manages the hardware resources more efficiently.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2014.06a
• /
• pp.206-208
• /
• 2014

본 논문에서는 HEVC (High Efficiency Video Coding)의 IDCT (Inverse Discrete Cosine Transform) 모듈을 AVX2 (Advanced Vector Extensions 2) 명령어 셋을 사용하여 고속화하는 방법을 제안한다. 제안하는 방법은 4 개의 $4{\times}4$ 블록을 AVX2 레지스터에 로드 한 후, 동시에 AVX2 명령어 셋을 통해 한 번에 IDCT 를 수행한다. 제안하는 방법은 $4{\times}4$ 블록 단위로 순차적으로 SIMD(Single Instruction Multiple Data) 명령어 셋을 통해 IDCT 를 수행하는 방법에 비해 명령어 단위의 병렬화 성능을 극대화한다. 실험 결과, HEVC 디코더의 $4{\times}4$ IDCT 에 SIMD 명령어 셋을 적용한 경우 기존의 HM-12.1 에 비해 평균 3.35 배 수행 속도를 향상 시킨 반면, 제안하는 방법은 HM12.1에 비해 평균 9.50 배 수행 속도를 향상 시켰다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.162-164
• /
• 2010

H.264/AVC(Advanced Video Coding) is a standard for video compression. H.264/AVC provides good video quality at substantially lower bit rates than previous standards. In this papers, we propose the efficient architecture of H.264/AVC decoder using GPGPU. GPGPU can process many of operation in parallel. IQ/IDCT is possible that parallel processing in H.264/AVC decoding algorithm.

• Proceedings of the KIEE Conference
• /
• 2007.10a
• /
• pp.371-372
• /
• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.2C
• /
• pp.113-123
• /
• 2007

In Ubiquitous communication environment, various conversions of images are essential, and most digital images are compressed by standard methods such as the Joint Photographic Expert Group (JPEG) and Motion Picture Expert Group (MPEG) which are based on the discrete cosine transform (DCT). In this paper, various image resizing algorithms in the DCT domain are analyzed, and a new image resizing algorithm, which shows superior performance compared with the conventional methods, is proposed. For arbitrary-ratio image resizing in the DCT domain, several blocks of $8{\times}8$ DCT coefficients are converted into one block using the conversion formula in the proposed algorithm, and the size of the inverse discrete cosine transform (IDCT) is decided optimally. The performance is analyzed by comparing the peak signal to noise ratio (PSNR) between original images and converted images. The performance of the proposed algorithm is better than that of the conventional algorithm, since the correlation of pixels in images is utilized more efficiently.

• Proceedings of the IEEK Conference
• /
• 2000.07b
• /
• pp.811-814
• /
• 2000

It this paper a VLSI architecture of the Shape-Adaptive Discrete Cosine Transform (SA-DCT) is described, which can be employed dedicatedly for MPEG-4 video codec. Adopting a fast DCT algorithm, the number of multipliers can be reduced by half in comparison with a conventional algorithm. This SA-DCT core with a small additional amount of hardware can perform the SA-Inverse DCT (SA-IDCT) by sharing multipliers and a transportation memory. The proposed SA-DCT core is integrated with 40,000 gates by using 0.35$mu$m triple-metal CMOS technology, which operates at 20 Mhz, and hence enables the realtime codec of CIF ($352{\times}288$ pixels) pictures.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2013.06a
• /
• pp.113-116
• /
• 2013

최근 방송, 의료, 우주산업, 게임, UCC, 핸드폰 등 여러 사업 분야에 걸쳐 실제에 근접한 영상을 요구하고 있고 이것은 3D와 Ultra High Definition (UHD) 영상의 출현으로 현실화 되고 있다. UHD 급에 걸맞는 압축률을 위해 Joint Collaborative Team on Video Coding (JCT-VC) 에서는 MPEG-4 Part 10 AVC/H.264를 뒤이을 차세대 코덱으로 High Efficiency Video Coding (HEVC) 를 개발을 시작했다. HEVC는 기존 MPEG-4 Part 10 AVC/H.264코덱과 비교해 40%이상의 압축률을 나타내지만 복잡도 역시 상승했다. 특히 복호화기에서 복잡도는 중요한 요소이며, 역 코사인변환 (Inverse Discrete Cosine Transform, IDCT) 은 전체 복호화시간의 8% ~ 16%를 차지하는 알고리즘이다. 본 논문에서는 IDCT 의 수행시간을 줄이기 위해 병렬프로그래밍 중의 하나인 SIMD명령어를 사용하여 효율적으로 병렬화 프로그래밍을 하는 기법들을 제안한다. 본 제안 기법은 IDCT 수행시간을 평균 59% 단축하는 결과를 보였다.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.3
• /
• pp.880-894
• /
• 1997

In this paper,we propose a new algorithm to perform DCT(Discrete Cosine Transform) withn the area reduced by prdeicting position of quantization coefficients to be zero.This proposed algorithm not only decreases the enoding time and the decoding time by reducing computation amount of FDCT(Forward DCT)and IDCT(Inverse DCT) but also increases comprossion ratio by performing each diffirent horizontal- vereical zig-zag scan assording to the calssified block size for each block on the huffiman coeing.Traditional image coding method performs the samd DCT computation and zig-zag scan over all blocks,however this proposed algorthm reduces FDCT computation time by setting to zero insted of computing DCT for quantization codfficients outside classfified block size on the encoding.Also,the algorithm reduces IDCT computation the by performing IDCT for only dequantization coefficients within calssified block size on the decoding.In addition, the algorithm reduces Run-Length by carrying out horizontal-vertical zig-zag scan approriate to the slassified block chraateristics,thus providing the improverment of the compression ratio,On the on ther hand,this proposed algorithm can be applied to 16*16 block processing in which the compression ratio and the image resolution are optimal but the encoding time and the decoding time take long.Also,the algorithm can be extended to motion image coding requirng real time processing.

• Proceedings of the Korean Society of Computer Information Conference
• /
• 2009.01a
• /
• pp.241-244
• /
• 2009

최근 모바일폰에 500만 화소 이상의 카메라 모듈이 장착되는 등 모바일 장치에서 고해상도 영상의 인코딩 및 디코딩에 대한 요구가 크게 늘어남에 따라 저성능 시스템에서 실시간으로 동작하는 영상 코덱 구현에 대한 필요성이 증대되고 있다. 본 논문은 JPEG 디코딩의 마지막 단계인 컬러변환 과정에 대해 계산 복잡도를 최적화하는 기법을 제안하고 성능을 평가하였다. 제안된 기법은 JPEG 디코딩 과정에서 IDCT(Inverse Discrete Cosine Transform) 변환과 컬러변환 간의 선형성을 바탕으로 이들 연산 순서를 재배열함으로써 컬러변환 과정에서 요구되는 계산 횟수를 줄이고, 재배열된 부동소수점 연산에 대해 정수 맵핑을 적용하여 계산 복잡도를 줄임으로써 실행시간을 최적화하였다. 임베디드 시스템 개발 플랫폼에서의 성능 평가를 통해 제안된 기법이 기존의 컬러변환 기법들과 비교하여 실행시간을 크게 단축함을 얄 수 있었으나 복원 영상의 화질이 상대적으로 저하됨을 확인하였다.