• Proceedings of the Korea Multimedia Society Conference
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• 2003.05b
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• pp.14-18
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• 2003

This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT(Discrete Cosine Transform/Inverse Discrete Cosine Transform). For the real time process of image data, it is required that high speed operation and small size hardware In the proposed architecture, the area of hardware is reduced by using the DA(distributed arithmetic) method and applying the concepts of pipeline on the parallel architecture. As a results, the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared as the non-pipeline architecture. And the operation speed is improved about 50％ up. The design for the proposed pipeline architecture of DCT/IDCT is coded using VHDL.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1823-1826
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• 2002

On modern computer culture, the high quality data is required in multimedia systems. So, the technology of data compression fur data transmission is necessary now. This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT (Discrete Cosine Transform/Inverse Discrete Cosine Transform. In the proposed architecture, the area of hardware is reduced by using the DA (distributed arithmetic) method and applies the concepts of pipeline to the parallel architecture. As a result the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared with the non-pipeline architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1433-1443
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• 1993

DCT(Discrete Cosine Transform) / IDCT(Inverse DCT) is widely used in various image compression and decompression systems as well as in DSP(Digital Signal Processing) applications. Since DCT/ IDCT is one of the most complicated part of the compression system, the performance of the system can be greatly enchanced by improving the speed of DCT/IDCT operation. In this thesis, we designed a DCT/IDCT core processor using module generator technique. By utilizing the partial sum and DA(Distributed Arithmetic) techniques, the DCT/ IDCT core processor is designed within small area. It is also designed to perform the IDCT(Inverse DCT) operation with little additional circuitry. The pipeline structure of the core processor enables the high performance, and the high accuracy of the DCT/IDCT operation is obtained by having fewer rounding stages. The proposed design is independent of design rules, and the number of the input bits and the accuracy of the internal calculation coa be easily adjusted due to the module generator technique. The accuracy of the processor satisfies the specifications in CCITT recommendation H, 261.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2701-2722
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• 2017

Key generation is essential for protecting wireless networks. Based on wireless channel reciprocity, transceivers can generate shared secret keys by measuring their communicating channels. However, due to non-simultaneous measurements, asymmetric noises and other interferences, channel measurements collected by different transceivers are highly correlated but not identical and thus might have some discrepancies. Further, these discrepancies might lead to mismatches of bit sequences after quantization. The referred mismatches significantly affect the efficiency of key generation. In this paper, an efficient key generation scheme leveraging wireless channel reciprocity is proposed. To reduce the bit mismatch rate and enhance the efficiency of key generation, the involved transceivers separately apply discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) to pre-process their measurements. Then, the outputs of IDCT are quantified and encoded to establish the bit sequence. With the implementations of information reconciliation and privacy amplification, the shared secret key can be generated. Several experiments in real environments are conducted to evaluate the proposed scheme. During each experiment, the shared key is established from the received signal strength (RSS) of heterogeneous devices. The results of experiments demonstrate that the proposed scheme can efficiently generate shared secret keys between transceivers.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.103-114
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• 1994

This paper proposes an implementation of DCT (Discrete Cosine Transform) and IDCT (Inverse DCT) using a fast DCT algorithm with shift and addition operations instead of multiplications Based on the proposed algorithm, a new VLSI architecture for the DCT and the IDCT is proposed. It shows modularity , regularity and capability for multiprocessing. Its performance is also simulated by a simulation software, "Compass". The results of the simulation provide the quality of decompression images, the increase in processing speed, representing the superiority of the proposed architecture.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.3
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• pp.97-103
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• 2008

In this paper, $256{\times}256$ input image is classified into a validity block and an edge block of $8{\times}8$ block for image compression. DCT(Discrete Cosine Transform) is executed only for the DC coefficient that is validity coefficients for a validity block. Predict the position where a quantization coefficient becomes 0 for an edge block, I propose new algorithm to execute DCT in the reduced region. Not only this algorithm that I proposed reduces computational complexity of FDCT(Forward DCT) and IDCT(Inverse DCT) and decreases encoding time and decoding time. I let compressibility increase by accomplishing other stability verticality zigzag scan by the block size that was classified for each block at the time of huffman encoding each. In addition, the algorithm that I suggested reduces Run-Length by accomplishing the level verticality zigzag scan that is good for a classified block characteristic and, I offer the compressibility that improved thereby.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.1
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• pp.84-89
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• 2019

JPEG is a most widely used standard image compression technology. This research introduces the JPEG image compression algorithm and describes each step in the compression and decompression. Image compression is the application of data compression on digital images. The DCT (discrete cosine transform) is a technique for converting a time domain to a frequency domain. First, the image is divided into 8 by 8 pixel blocks. Second, working from top to bottom left to right, the DCT is applied to each block. Third, each block is compressed through quantization. Fourth, the matrix of compressed blocks that make up the image is stored in a greatly reduced amount of space. Finally if desired, the image is reconstructed through decompression, a process using IDCT (inverse discrete cosine transform). The purpose of this research is to review all the processes of image compression / decompression using the discrete cosine transform method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.180-181
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• 2018

JPEG is a most widely used standard image compression technology. This research introduces the JPEG image compression algorithm and describes each step in the compression and decompression. Image compression is the application of data compression on digital images. The DCT (discrete cosine transform) is a technique for converting a time domain to a frequency domain. First, the image is divided into 8 by 8 pixel blocks. Second, working from top to bottom left to right, the DCT is applied to each block. Third, each block is compressed through quantization. Fourth, the array of compressed blocks that make up the image is stored in a greatly reduced amount of space. Finally if desired, the image is reconstructed through decompression, a process using IDCT (inverse discrete cosine transform).

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.2074-2079
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• 2018

Global state space's optimal policy is used for offline controller in the form of table by using Dynamic Programming. If an optimal policy table has a large amount of control data, it is difficult to use the system in a low capacity system. To resolve these problem, controller using the compressed optimal policy table is proposed in this paper. A DCT is used for compression method and the cosine function is used as a basis. The size of cosine function decreased as the frequency increased. In other words, an essential information which is used for restoration is concentrated in the low frequency band and a value of small size that belong to a high frequency band could be discarded by quantization because high frequency's information doesn't have a big effect on restoration. Therefore, memory could be largely reduced by removing the information. The compressed output is stored in memory of embedded system in offline and optimal control input which correspond to state of plant is computed by interpolation with Inverse DCT in online. To verify the performance of the proposed controller, computer simulation was accomplished with a one link inverted pendulum.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1062-1070
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• 2002

In this paper, variable radix-two multibit coding algorithm is presented and applied in the implementation of discrete cosine transform(DCT) and inverse discrete cosine transform(IDCT). Variable radix-two multibit coding means the 2k SD (signed digit) representation of overlapped multibit scanning with variable shift method. SD represented by 2k generates partial products, which can be easily implemented with shifters and adders. This algorithm is most powerful for the hardware implementation of DCT/IDCT with constant coefficient matrix multiplication. This paper introduces the suggested algorithm, it's proof and the implementation of DCT/IDCT The implemented IDCT chip with 8 PEs(Processing Elements) and one transpose memory runs at a tate of 400 Mpixels/sec at 54MHz frequency for high speed parallel signal processing, and it's verified in HDTV and MPEG decoder.