• Journal of Computing Science and Engineering
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• v.9 no.2
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• pp.108-117
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• 2015

Interrupt handling is generally separated from process scheduling. This can lead to a scheduling anomaly and priority inversion. The processor can interrupt a higher priority process that is currently executing, in order to handle a network packet reception interruption on behalf of its intended lower priority receiver process. We propose a new network interrupt handling scheme that combines interrupt handling with process scheduling and the priority of the process. The proposed scheme employs techniques to identify the intended receiver process of an incoming packet at an earlier phase. We implement a prototype system of the proposed scheme on Linux 2.6, and our experiment results show that the prototype system supports the predictable real-time behavior of higher priority processes even when excessive traffic is sent to lower priority processes.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1947-1953
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• 2011

OSEK/VDX is a joint project aiming at an industry standard for ECUs in vehicles and OSEK OS is a real-time operating system that meets OSEK/VDX specifications. In this paper, we suggest an implementation of task switching and interrupt handling mechanisms of OSEK operating system based on ARM processors. Considering the requirements of OSEK OS and characteristics of ARM processor, we have designed task switching and interrupt handling mechanisms. For evaluating the validation of the suggested mechanisms, we have checked the functional correctness on an experimental embedded board with ARM processor and calculated the time of task switching and interrupt handling.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.319-321
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• 2003

인터럽트는 시스템의 내.외부의 프로그램 또는 장치에 의해 발생하는 신호로서 운영체제가 하던 일을 멈추고 인터럽트 서비스 루틴(Interrupt Service Routine)을 통해 적합한 동작을 수행하도록 한다. 실시간 시스템을 포함한 대부분의 컴퓨팅 시스템에서 인터럽트의 발생 빈도와 인터럽트 서비스 루틴의 수행시간에 따라 Response Time이 길어질 수 있는데 이는 시스템에 커다란 오버헤드가 된다. 본 논문에서는 실시간 운영체제에서 Response Time을 줄이고 효율적으로 인터럽트를 서비스하기 위한 인터럽트 서비스 프로세스의 구현에 대해 기술한다.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.4
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• pp.437-441
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• 2010

A new application area in which wireless sensor networks are applied requires the performance of more elaborated and complicated task and the completion of those tasks within a time limit. Until now, it is, however, insufficient to do research on the mechanism of handling interrupt based on real-time sensor operating systems which carefully consider the limitation of resources of sensor nodes and the property of tasks which is executed in a wireless sensor network area. In this paper, the requirements satisfying real-time in sensor operating systems are analyzed and based on this, a system is designed and implemented. In addition, the proposed mechanisms are confirmed by several verification methods, and the efficiency of the performance and the satisfaction of those requirements for real-time are verified by simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.141-151
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• 1994

this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.63-69
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• 2019

Recently, ultra-low latency flash storage devices such as Z-SSD and Optane SSD were introduced with the significant technological improvement in the storage devices which provide much faster response time than today's other NVMe SSDs. With such ultra-low latency, $10{\mu}s$, storage devices the cost of context switch could be an overhead during interrupt-driven I/O completion process. As an interrupt-driven I/O completion process could bring an interrupt handling overhead, polling or hybrid-polling for the I/O completion is known to perform better. In this paper, we analyze tail latency problem in a polling process caused by process scheduling in data center environment where multiple applications run simultaneously under one system and we introduce our adaptive polling selection technique which dynamically selects efficient processing method between two techniques according to the system's conditions.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.158-163
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• 1986

This article surveys techniques and issues related to real time process control system developed for industrial control applications. It covers the system architecture and software engineering issues such as the design of data structures, scheduling of asynchronous task activities, management of shared resources, handling of interrupt and implementing an user friendly man-machine interface. Also problems associated with implementing a real-time system that supports dynamic configuration of data base is addressed.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.457-459
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• 2000

최근 이동단말기나 PDA, 스마트폰과 같은 정보기기나 디지털 가전기기의 사용이 증대됨에 따라, ARM코어 시스템을 기반으로 하는 프로세서와 이를 운영하기 위한 소프트웨어 수요도 증가하고 있다. 본 논문은 프로세서를 운영하기 위한 소프트웨어 중에서 예외처리를 위한 일반적인 인터럽트 제어를 다룬다. ARM 시스템 상에서 임의의 주변 장치(타이머/카운터)에 의해 발생하는 인터럽트 처리 과정과 예외처리를 제어하기 위한 벡터 테이블을 구성하는 방법에 대해 분석한다. 그리고 인터럽트를 처리하는 인터럽트 코드부분과 벡터 테이블내의 인터럽트의 상호 연관성에 대해 논의한다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.183-189
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• 2019

Despite its low cost, ARM is widely used in smartphones, digital cameras, home network devices, and wireless technologies because of its low power consumption and reliable performance. The domestic memory semiconductor design technology is in the world's highest level, but that of the processor is far less than that, which results in the technology unbalance between the memory and the processor. When designing a processor, exception and interrupt capabilities are requisite, but this is often omitted in the research stage. However, exception processing and interrupts must be included in order for the processor to function fully. In this paper, we design a 32-bit ARMv4 family of processors with exception handling and interrupts using VHDL and verify with ModelSim. As a result, ARM's exception and interrupts are successfully performed.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.109-110
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• 2013

가상화 기술의 발전과 더불어 산업 전반에서 가상화 기술이 널리 사용되고 있지만 여전히 높은 장치 처리량을 요구하는 워크로드의 경우 가상화 환경에서 사용되지 못하고 있다. 가상머신의 I/O는 가상장치를 에뮬레이션 하는 가상화 오버헤드에 의해 장치 성능을 제약받고 있기 때문이다. 최근 가상머신에서 직접접근을 지원하는 장치의 등장으로 I/O 요청 중 발생하는 가상화 비용을 효과적으로 제거 하였지만, 장치 요청이 끝난 후 발생하는 인터럽트를 가상머신이 처리하는 과정에서 발생하는 비용이 여전히 성능을 제약하고 있다. 이에 본 논문에서는 인터럽트 과정의 비용을 줄이기 위한 인터럽트 전용가상 프로세서 기법을 제안한다.