• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.142-151
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• 1995

The trend of compact size, light weight, low power consumption in the portable telecommunication equipments demands large scale integration and low voltage operation of chips and the minimization of the number of the components in the telecommunication terminal. According to the trend, existing chip components are modulized and are integrated as a part into a bigger chip. This paper is about the development of the peripheral units of micro-controller for mobile telecommunication terminal. Peripherals consist of DMA controller, Interrupt controller, timer, watchdog timer, clock generator, and power management unit. They are designed to be integrated with EU(Execution Unit) and BIU(Bus Interface Unit) into a 16 bit micro-controller which will be used as a core of an ASIC for next generation digital mobile telecommunication terminal. At first, whole block of the micro-controller was described by VHDL behavioral model and simulated to verify its overall operation. Then, watchdog timer, clock generator and power management unit were directly synthesized by using VHDL synthesis tool. Rest of the pheriperal units were designed and simulated by using Compass Design Tool.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.12
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• pp.1125-1131
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• 2013

Nowadays, embedded software development using the MATLAB/Simulink system is gradually emerging. Studies generating the parts of embedded S/W in a Rapid Prototype are presented. In this paper, a method to generate the entire embedded S/W of enhanced AC motor control is proposed. High performance motor control could not be achieved with the basic Simulink library and RAppID Toolbox library as it does not have PWM based Interrupt, an ASAC (Analog Sensing for AC Motors) function and other special functions of the Freescale MPC555x. Consequently, the required libraries for enhanced AC motor control are created by Legacy code tool, TLC (Target Language Compiler) and S-Function (System-Function) of MATLAB/ Simulink and utilized in the Rapid Prototype. Motor control performance and execution time are compared automatically to the generated-code S/W with the hand coded S/W. The IPMSM (Interior Permanent Magnet Synchronous Motor) and MPC5553 board that were designed as the AC motor controller for hybrid electrical vehicle are used for the test. The performances meet the requirements and satisfactory results are acquired.

• Journal of KIISE
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• v.42 no.5
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• pp.551-557
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• 2015

The technology using ARM TrustZone draws attention as a new embedded virtualization approach. The ARM TrustZone defines two virtual execution environment, the secure world and the normal world. In such an environment, the inter-world communication is important to extend function of software. However, the current monitor software does not sufficiently support the inter-world communication. This paper presents a new inter guestOS communication scheme, for each world, for the ARM TrustZone virtualization. The proposed communication scheme supports bidirectional inter-world communication for single core and multicore environment. In this paper, It is implemented on a NVIDIA Tegra3 processor based on the ARM Cortex-A9 MPCore and it showed a bandwidth of 30MB/s.

• Journal of IKEEE
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• v.23 no.3
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• pp.1068-1076
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• 2019

Most of the electronics we use today have built-in microcontrollers, which are called embedded systems. In such a small environment, responsiveness is very important for the microcontroller. In this paper, the basic input/output control, timer/counter interrupt operation principle, and understanding of the microcontroller are described. Program logic is proposed to improve throughput and latency by controlling characteristics of service routine and program execution order. The hardware simulations in this paper were verified using ATmega128 and PIC16F877A from Atmel and Microchip.

• Journal of Astronomy and Space Sciences
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• v.29 no.3
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• pp.315-320
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• 2012

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 $MeVcm^2/mg$. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.

• The Journal of the Korea Contents Association
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• v.11 no.9
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• pp.45-53
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• 2011

According to the necessity of measuring equipments for advanced military systems, real-time characteristics such as time determinism and execution accuracy pursuing low-latencies have become very important. With this reason, the market demand for real-time features in the general purpose operating system such as Linux has been enlarging. To meet these requirements, RTLinux and RTAI has been developed as dual-kernels based on Linux. However, developers should use assembler languages to facilitate real-time in RT-Linux, it is very difficult to deal with it. RTAI has disadvantage that it only provides soft real-time. To solve these problems, RTiK-Linux was developed. In this paper, we propose a new dual-kernel with hard real-time capabilities in Linux, called RTiK-Linux(Real-Time implemented Kernel for Linux). We first introduce related researches and then describe the design methodologies to guarantee the resolution which almost accords with the timer settings. Finally, we present the results of experimental measurements and analyze them in order to validate and evaluate the proposed RTiK-Linux.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.429-438
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• 2001

GPS (Global Positioning System) is the most ideal navigation system which can be used on the earth irrespective of time and weather conditions. GPS has been used for various applications such as construction, survey, environment, communication, intelligent vehicles and airplanes and the needs of GPS are increasing in these days. This paper deals with the design and implementation of the RTOS (Real-Time Operating System) for a GPS navigation computer in the GPS/INS integrated navigation system. The RTOS provides the optimal environment for execution and the base platform to develop GPS application programs. The key facilities supplied by the RTOS developed in this paper are priority-based preemptive scheduling policy, dynamic memory management, intelligent interrupt handling, timers and IPC, etc. We also verify the correct operations of all application tasks of the GPS navigation computer on the RTOS and evaluate the performance by measuring the overhead of using the RTOS services.

• The Transactions of the Korea Information Processing Society
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• v.4 no.10
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• pp.2581-2595
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• 1997

In this paper, the real-time facility of the operating system for a VOD(Video On Demand) server have been analyzed and implemented. The requirements of the real-time scheduling have been gathered by analyzing the model of the video-data-transfer-path. Particularly, the influence of the bottleneck subsystem have been analyzed. Thus, we have implemented the real-time scheduler and primitives which is proper for processing the digital video. In performance measurements, the degree of the guarantee of the real-time scheduler have been experimented. The measured data show that the most time constraints of the process is satisfied. But, the network protocol processing by the interrupt is a major obstacle of the real-time scheduling. We also have compared the difference between the real-time scheduler and the non-real-time scheduler by measuring the inter-execution time. According to the measured results, the real-time scheduler should be used for efficient video service because the processor time allocated to the process can't be estimated when the non-real-time scheduler is used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.9
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• pp.1405-1411
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• 2022

Power management is still an important issue in embedded environments as hardware advances like high-performance processors. Power management methods such as DVFS control CPU frequencies in an adaptive manner for efficient power management in polling-based I/O programs such as network communication. This paper presents the problems of the existing power management method and proposes a new power management method. Through this, it is possible to reduce electric consumption by increasing the polling cycle in situations where the frequency of data reception is low, and on the contrary, in situations where data reception is frequent, it can operate at the maximum frequency without performance degradation. After implementing this as a code layer on the embedded board and observing it through Atmel's Power Debugger, the proposed method showed a performance improvement of up to 30% in energy consumption compared to the existing power management method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.