• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.34.6-34
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• 2002

1. Introduction 2. System Configuration 2.1 Control System 2.1.1 Longitudinal control 2.1.2 Lateral control 2.2 Sensor System 2.2.1 Photo interrupt 2.2.2 Ultrasonic sensor 2.3 Vision system 2.4 Communication system 2.4.1 Data communication 2.4.2 Image Communication 3. Test and Result 3.1 Vision test 3.2 Ultrasonic sensor test 4. Conculsion. Acknowledgment References.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.120-123
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• 2000

In this paper, A target architecture and interface synthesizer are proposed for processor-embedded codesign. The target architecture has the form of ARM processor based on AMBA. The interface synthesizer automatically generates an interface circuit for the communication between HW and SW. A memory map is used as the communication channel and an interrupt-based interface is applied for synchronized communication between HW and SW modules. In order to verify the function and performance of proposed target architecture and the interface synthesizer, practical test example is applied. Experimental results show the proposed interface synthesizer functioned correctly in the HW/SW codesign environment.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.158-163
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• 1986

This article surveys techniques and issues related to real time process control system developed for industrial control applications. It covers the system architecture and software engineering issues such as the design of data structures, scheduling of asynchronous task activities, management of shared resources, handling of interrupt and implementing an user friendly man-machine interface. Also problems associated with implementing a real-time system that supports dynamic configuration of data base is addressed.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.193-194
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• 2009

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.53-56
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• 2003

Ethernet is one of the most successful LAN technologies. Now gigabit ethernet is available in real network and some network interface cards(NIC) supports TCP segment offloading (TSO), IP checksum offloading(ICO), Jumbo frame and interrupt moderation. If we use this features appropriately, we obtain high throughput with low CPU utilization. This paper represents the network performance by varying above features.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.601-602
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• 2015

Interruption of AC is easier due to natural occuring of zero crossings. In DC, zero crossings is achieved by Forced commutation technique. In this paper an alternative counter voltage(ACV) DC Hybrid Circuit breaker(DC-HCB) is modeled using EMTP/ATP tool, Results show that, ACV DC-HCB can interrupt DC with in 5ms with a source voltage of upto 1 KV.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2011.10a
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• pp.80-80
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• 2011

본 논문은 윈도우에 디바이스 드라이버 형태로 동작하는 실시간 이식 커널을 제안한다. x86하드웨어에서 제공하는 Local APIC(Advanced Programmable Interrupt Controller)를 이용하여 윈도우와는 별도의 타이머를 제공하여, 독립적인 타이머 인터럽트를 통해 실시간성이 필요한 서비스가 정확한 주기로 동작하여 마감시한을 보장한다. 그리고 1553b 통신에서 IP470을 통해 오실로 스코프로 테스트하여 제안한 실시간 이식 커널이 실시간성을 보장함을 보인다.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.36-38
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• 2002

Low voltage circuit breakers which interrupt rapidly and raise the reliability of power supply are widly used in power distribution systems. In the paper, it was investigated how much Interrupting capability was improved by correcting the shape of the contact system in molded case circuit breaker(below MCCB), Prior to the interrupting testing, it was necessary for the optimum design to analyze magnetic forces on the contact system, generated by current and flux density. This paper presents both our compuational analysis and test results contact system in MCCB.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10a
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• pp.617-619
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• 2000

본 논문에서는 일반 사용자 수준에서 시스템 호출을 제어하는 기법을 제안하고 이를 위한 유닉스 기반 시스템에서 시스템 호출을 인터럽트 하는 기법을 기술한다. 제안된 방법은 OS 소스코드의 수정을 요구하지 않고 동적으로 적용이 가능하다. 또한 시스템 호출 제어기법의 응용으로 사용자의 시스템 자원 접근 및 권한을 제어하는 보안모델인 UPS (Unix Protection System)에 대하여 기술한다.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.29-29
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• 2000

This paper describes the design and implementation of a high-speed navigation computer to achieve precision navigation performance with Strapdown INS. The navigation computer inputs are velocity and angular increment data from the ISA at the signal of the 2404Hz interrupt and performs the removal of gyro block motion and the compensation of high dynamic errors at the 200Hz. For high-speed and high-accuracy, the computer consists of the 68040 micro-processor, 128k Memories, FPGAs, and so on. We show that the computer satisfies the required performance by In-Run navigation tests.