• Journal of Power Electronics
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• v.8 no.3
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• pp.275-279
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• 2008

An LLC series resonant converter has many unique characteristics and improvements over PWM topologies. However, many output capacitors are needed in parallel to satisfy output voltage ripple and the rated ripple current of the capacitors. This paper deals with a novel two phase interleaved LLC resonant converter using a phase of the resonant capacitor. The proposed converter can satisfy output voltage ripple and a rated ripple current of capacitors with few output capacitors, relatively. The operation and features are considered in detail and a prototype with a 12V-100A output is investigated.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.526-528
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• 2008

LLC series resonant converter has many unique characteristics and improvement over PWM topologies. However, many output capacitors should be needed in parallel to satisfy an output voltage ripple and a rated ripple current of the capacitors. This paper is deal with a novel two phase interleaved LLC resonant converter using a phase of the resonant capacitor. The proposed converter can satisfy output voltage ripple and a rated ripple current of capacitors with few output capacitors, relatively. The operation and features is considered in detail and a prototype with a 12V-100A output is investigated.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.48-58
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• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• Journal of Industrial Technology
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• v.32 no.A
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• pp.39-45
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• 2012

In this paper the digital control scheme of interleaved PFC for 3-phase modular UPS is presented. The interleaved PFC is composed of two identical PFC connected in parallel and each PFC is controlled by the interleaved switching signals which have the same switching frequency and the $180^{\circ}$ phase difference. As a consequence of the interleaving operation, the Interleaved PFC exhibits both lower current ripple at the input side and lower voltage ripple at the outside. Therefore, the switching and conduction losses as well as EMI levels can be significantly decreased. Simulation and experimental results verify the usefulness of the interleaved PFC.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.6
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• pp.484-489
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• 2020

This study proposes a new soft-switching three-level flying capacitor converter with low filter inductance. The proposed converter can achieve zero voltage switching (ZVS) turn-on of all switches by using auxiliary components La and Ca. It can also reduce filter inductance because the applied voltage of the filter inductor is decreased by using the flying capacitor. Furthermore, filter inductance can be reduced because the operating frequency of the filter inductor is doubled by the phase shifting between switches S3 and S4. The operation principle, design of passive components for ZVS turn-on, interleaving effects, and comparison of different topologies are presented. The experimental waveforms of a 1 kW two-phase interleaved converter prototype are provided to verify the validity of the proposed converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.5
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• pp.384-390
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• 2022

In this study, a single-stage, four-phase, interleaved, totem-pole AC-DC converter is proposed for a super-fast charger station that requires high power, a wide voltage range, and bidirectional operation capabilities and adopts various types of electric transport vehicles. The proposed topology is based on current-fed push-pull dual active bridge converter combined with the totem-pole operation. Owing to the four-phase interleaving effect, the bridge on the grid side can switch at 0.25, 0.5, and 0.75 to achieve a ripple-free grid current. The input filter can be removed theoretically. Switching methods for the duty of the secondary-side duty cycle are proposed, and they correspond to the primary duty cycle for reducing the circulating power and handling the total harmonic distortion. Therefore, the converter can operate under a wide voltage range. Experimental results from a 7.5 kW prototype are used to validate the proposed concept.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.4
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• pp.403-411
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• 2013

This paper proposes an isolated bidirectional three-phase push-pull dc-dc converter for high power application such as eco-friendly vehicles, renewable energy systems, energy storage systems, and solid-state transformers. The proposed converter achieves ZVS turn-on of all switches and volume of passive components is small by an effect of three-phase interleaving. The proposed converter has identical switching pattern for both boost and buck mode, and therefore can provide seamless characteristic at the mode transition. A 3kW prototype of the proposed converter has been built and tested to verify the validity of the proposed operation.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1211-1222
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• 2018

This study presents a power distribution control scheme for a three-phase interleaved parallel DC/DC converter in a battery energy storage system. To extend battery life and increase the power equalization rate, a control method based on the nth order of the state of charge (SoC) is proposed for the charging and discharging processes. In the discharging process, the battery sets with high SoC deliver more power, whereas those with low SoC deliver less power. Therefore, the SoC between each battery set gradually decreases. However, in the two-stage charging process, the battery sets with high SoC absorb less power, and thus, a power correction algorithm is proposed to prevent the power of each particular battery set from exceeding its rated power. In the simulation performed with MATLAB/Simulink, results show that the proposed scheme can rapidly and effectively control the power distribution of the battery sets in the charging and discharging processes.

• ETRI Journal
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• v.31 no.6
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• pp.795-802
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• 2009

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT-DMB) baseband receiver SoC. The AT-DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T-DMB system; therefore, a conventional T-DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT-DMB baseband receiver SoC is fabricated using 0.13 ${\mu}m$ technology and shows successful operation with a 50 mW power dissipation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.6 no.4
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• pp.3-38
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• 1996

The mobile station shall convolutionally encode the data transmitted on the reverse traffic channel and the access channel prior to interleaving. Code symbols output from the convolutional encoder are repeated before being interleaved except the 9600 bps data rate. All the symbols are then interleaved, 64-ary orthogonal modulation, direct-sequence spreading, quadrature spreading, baseband filtering and QPSK transmission. The sync, paging, and forward traffic channel except the pilot channel in the forward CDMA channel are convolutionally encoded, block interleaved, spread with Walsh function at a fixed chip rate of 1.2288 Mcps to provide orthogonal channelization among all code channels. Following the spreading operation, the I and Q impulses are applied to respective baseband filters. After that, these impulses shall be transmitted by QPSK. Authentication in the CDMA system is the process for confirming the identity of the mobile station by exchanging information between a mobile station and the base station. The authentication scheme is to generate a 18-bit hash code from the 152-bit message length appended with 24-bit or 40-bit padding. Several techniques are proposed for the authentication data computation in this paper. To protect sensitive subscriber information, it shall be required enciphering ceratin fields of selected traffic channel signaling messages. The message encryption can be accomplished in two ways, i.e., external encryption and internal encryption.