• 전기학회논문지P
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• 제65권4호
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• pp.303-308
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• 2016

A light-emitting diode (LED) has been increasingly applied to various industrial fields and general lightings because of its high efficiency, low power consumption, environment-friendly characteristic and long lifetime. To drive this LED lighting, various types of power converters have been applied. Also, power factor correction (PFC) techniques play an important role in the power supply technology. In this paper, design and control of a DCM interleaved boost PFC converter is discussed. The proposed converter can reduce current ripples at input and output side by cancelling an each phase of inductor currents. Since the IC does not require the auxiliary winding of inductor for current detection, simple PFC circuit is achieved. Therefore, it contributes to increase efficiency and downsize the whole system volume, cost. Also, the performance of the proposed system is demonstrated through experiments.

• 전기학회논문지
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• 제64권9호
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• pp.1306-1314
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• 2015

This paper deals with a switching method of a three-phase interleaved bidirectional DC-DC converter to obtain high efficiency in wide load range. The proposed soft-switching method provides ZVS and ZCS at turn-on, and ZVS at turn-off of the switch as well as considerably reduced conduction loss in light load. Simulation and experiment are carried out with a bidirectional DC-DC converter having the power rating of 3 [kW], and those results show the validity of the proposed switching method.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 전력전자학술대회 논문집
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• pp.403-404
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• 2013

In this paper, a PCS which consists of high boost interleaved full-bridge converter and single phase half-bridge inverter is proposed. Proposed PCS is using two full bridge converter modules. PCS consists of parallel input / serial output. It can reduce turn ratio of high frequency transformer. In this paper, PCS which is using 1.5[kW] interleaved full-bridge converter and single phase half bridge inverter is designed and verified stability of system through experiment.

• Journal of Electrical Engineering and Technology
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• 제5권2호
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• pp.319-328
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• 2010

In this paper, an optimal selection methodology for the number of phases will be proposed for an interleaved boost converter (IBC). Also, the analysis of the input current ripple according to CCM and DCM is carried out. The proposed design methodology will be theoretically analyzed, and its validity verified by simulation as well as with experimental results. Moreover, a comparison of cost and efficiency based on a 600W laboratory prototype using the Ballard NEXA 1.2kW PEMFC system is demonstrated.

• 전력전자학회논문지
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• 제13권4호
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• pp.257-262
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• 2008

본 논문에서는 임계 인덕터 전류모드로 동작하는 다상 교호 승압컨버터의 평균 상태방정식을 유도하고, 정상상태 해석 및 소 신호 제어특성을 고찰한다. 또한, 유도된 수식 이론을 근거로, 800W급 2상 교호 승압컨버터를 제작하고, 60인치용 PDP 파워모듈의 PFC 블록에 적용함으로서, 제안된 방식의 실효성을 검증한다.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1632-1642
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• 2014

This paper presents an interleaved resonant converter to reduce the voltage stress of power MOSFETs and achieve high circuit efficiency. Two half-bridge converters are connected in series at high voltage side to limit MOSFETs at $V_{in}/2$ voltage stress. Flying capacitor is used between two series half-bridge converters to balance two input capacitor voltages in each switching cycle. Variable switching frequency scheme is used to control the output voltage. The resonant circuit is operated at the inductive load. Thus, the input current of the resonant circuit is lagging to the fundamental input voltage. Power MOSFETs can be turn on under zero voltage switching. Two resonant circuits are connected in parallel to reduce the current stress of transformer windings and rectifier diodes at low voltage side. Interleaved pulse-width modulation is adopted to decrease the output ripple current. Finally, experiments are presented to demonstrate the performance of the proposed converter.

• 전력전자학회논문지
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• 제12권2호
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• pp.123-130
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• 2007

본 논문에서는 불연속 인덕터 전류모드에서의 다상 교호 강압 컨버터의 정상상태 해석 및 소신호 모델을 유도하여 일반화된 식을 제시한다. 컨버터의 제어기 설계를 위해서 필요한 완전한 차수 모델을 통한 소신호 모델의 전달함수를 유도하고 이를 통해 시스템의 동특성을 분석한다. 시뮬레이션 및 실험 결과를 통하여 이론에서 제시한 특성을 검증한다.

• Journal of Electrical Engineering and Technology
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• 제12권4호
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• pp.1529-1536
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• 2017

A digital dual-channel interleaved phase-shift full-bridge converter is investigated in this paper, and its topology and principle are analyzed. To realize current sharing and stabilize the output voltage, a controller with current sharing loop and closed voltage loop is employed. In addition, current sharing will increase the output current fluctuation and a new digital interleaved driving technology is proposed to reduce the output current ripple. To verify the analysis, simulation and experiments are carried out, which shows the effectiveness of the proposed control strategies.

• 한국산학기술학회논문지
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• 제17권10호
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• pp.600-608
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• 2016

본 논문은 저전압-고전류 사양을 갖는 전력변환 시스템에 적합한 고효율 인터리브드 방식의 위상천이 풀브릿지 컨버터를 제안한다. 제안하는 컨버터는 1차 측에 '3개의 스위치 브릿지와 2개의 트랜스포머', 2차 측에 '2개의 정류단'으로 구성되어 있다. 2개의 트랜스포머는 각각 동일한 크기의 전력변환을 담당하고, 서로가 위상 차이를 두고 에너지를 전달하는 특징을 갖는다. 이를 통해 기존의 인터리브드 방식의 위상천이 풀브릿지 컨버터 수준의 높은 시스템 안정성을 가지게 된다. 제안하는 컨버터는 기존 컨버터의 효율향상 한계로 작용하였던 lagging-leg 스위치의 하드스위칭 특성을 개선하기 위해 새로운 회로 구조와 제어기법을 적용하였다. 이를 통해 제안하는 컨버터는 기존 컨버터에 비해 하드스위칭 조건을 갖는 스위치의 수를 절반으로 줄였으며, 기존 컨버터에 비해 회로 구성에 사용되는 스위치의 수를 줄여 시스템의 복잡도를 개선하는 효과도 얻었다. 제안하는 컨버터의 특성을 확인하기 위해 본 논문에서는 저전압-고전류 특징을 갖는 3kW 서버용 전원장치 스펙을 이용하여 기존 컨버터와 제안하는 컨버터 시스템을 설계하였고, PSIM 시뮬레이션 툴을 활용하여 두 회로의 동작 특징을 비교하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.626-628
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• 2004

This paper describes an 8-bit CMOS folding A/D converter for set-top box. Modular low-power, high-speed CMOS A/D converter for embedded systems aims at design techniques for low-power, high-speed A/D converter processed by the standard CMOS technology. The time-interleaved A/D converter or flash A/D converter are not suitable for the low-power applications. The two-step or multi-step flash A/D converters need a high-speed SHA, which represents a tough task in high-speed analog circuit design. On the other hand, the folding A/D converter is suitable for the low-power, high-speed applications(Embedded system). The simulation results illustrate a conversion rate of 40MSamples/s and a Power dissipation of 80mW(only analog block) at 2.5V supply voltage.