• Structural Engineering and Mechanics
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• v.25 no.4
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• pp.383-403
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• 2007

The contact problem for an elastic layer resting on an elastic half plane is considered according to the theory of elasticity with integral transformation technique. External loads P and Q are transmitted to the layer by means of two dissimilar rigid flat punches. Widths of punches are different and the thickness of the layer is h. All surfaces are frictionless and it is assumed that the layer is subjected to uniform vertical body force due to effect of gravity. The contact along the interface between elastic layer and half plane will be continuous, if the value of load factor, ${\lambda}$, is less than a critical value, ${\lambda}_{cr}$. However, if tensile tractions are not allowed on the interface, for ${\lambda}$ > ${\lambda}_{cr}$ the layer separates from the interface along a certain finite region. First the continuous contact problem is reduced to singular integral equations and solved numerically using appropriate Gauss-Chebyshev integration formulas. Initial separation loads, ${\lambda}_{cr}$, initial separation points, $x_{cr}$, are determined. Also the required distance between the punches to avoid any separation between the punches and the layer is studied and the limit distance between punches that ends interaction of punches, is investigated. Then discontinuous contact problem is formulated in terms of singular integral equations. The numerical results for initial and end points of the separation region, displacements of the region and the contact stress distribution along the interface between elastic layer and half plane is determined for various dimensionless quantities.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2014.11a
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• pp.196-196
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• 2014

플라즈마 건식 식각 기술은 반도체 식각공정에서 효과적으로 이용되고 있으며, 반도체 소자의 크기가 줄어듬에 따라 미세하고 정확하게 식각 깊이를 제어할 수 있는 원자층 식각 기술이 개발되었다. 3-5족 반도체 소자의 Interface Passivation Layer 로 이용되는 $Al_2O_3$ 와 BeO 의 원자층 식각을 하였으며, 각각의 원자층 식각 조건과 식각 후의 표면 거칠기 변화에 대한 영향을 확인 할 수 있었다.

• Journal of Mechanical Science and Technology
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• v.20 no.2
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• pp.271-277
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• 2006

A numerical study is made of the spin-up from rest of a three-layer fluid in a closed, vertically-mounted cylinder. The densities in the upper layer $\rho_1$, middle layer $\rho_2$ and lower layer $\rho_3\;are\;\rho_3\;>\;\rho_2\;>\;\rho_1$, and the kinematic viscosities are left arbitrary. The representative system Ekman number is small. Numerical solutions are obtained to the time-dependent axisymmetric Navier-Stokes equations, and the treatment of the interfaces is modeled by use of the Height of Liquid method. Complete three-component velocity fields, together with the evolution of the interface deformations, are depicted. At small times, when the kinematic viscosity in the upper layer is smaller than in the middle layer, the top interface rises (sinks) in the central axis (peripheral) region. When the kinematic viscosity in the lower layer is smaller than in the middle layer, the bottom interface rises (sinks) in the periphery (axis) region. Detailed shapes of interfaces are illustrated for several cases of exemplary viscosity ratios.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.143.1-143.1
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• 2016

Ge is a promising candidate to replace Si in MOSFET because of its superior carrier mobility, particular that of the hole. However Ge oxide is thermodynamically unstable. At elevated temperature, GeO is formed at the interface of Ge and GeO2, and its formation increases the interface defect density, degrading its device performance. In search for a method to surmount the problem, we investigated Ge oxidation through an inert capped oxide layer. For this work, we prepared low doped n-type Ge(100) wafer by removing native oxide and depositing a capping layer, and show that GeO2 interface can be successfully grown through the capping layer by thermal oxidation in a furnace. The thickness and quality of thus grown GeO2 interface was examined by ellipsometry, XPS, and AFM, along with I-V and C-V measurements performed at 100K to 300K. We will present the result of our investigation, and provide the discussion on the oxide growth rate, interface state density and electrical characteristics in comparison with other studies using the direct oxidation method.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.1081-1081
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• 2002

Top emission organic EL devices were fabricated by using metal-doped cathode interface layer to achieve low drive voltages. Also, facing-targets-type sputtering was used to sputter indium-tin oxide layer on top of organic active layer. The devices fabricated in this study showed reasonably high external quantum efficiency of about 1 % which is comparable to that of bottom-emission-type devices.

• Structural Engineering and Mechanics
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• v.64 no.1
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• pp.71-79
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• 2017

In this study, interaction of several interface cracks located between a functionally graded material (FGM) layer and an elastic layer under anti-plane deformation based on the distributed dislocation technique (DDT) is analyzed. The variation of the shear modulus of the functionally graded coating is modeled by an exponential and linear function along the thickness of the layer. The complex Fourier transform is applied to governing equation to derive a system of singular integral equations with Cauchy type kernel. These equations are solved by a numerical method to obtain the stress intensity factors (SIFs) at the crack tips. The effects of non-homogeneity parameters for exponentially and linearly form of shear modulus, the thickness of the layers and the length of crack on the SIFs for several interface cracks are investigated. The results reveal that the magnitude of SIFs decrease with increasing of FG parameter and thickness of FGM layer. The values of SIFs for FGM layer with exponential form is less than the linear form.

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.33-35
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• 2006

The interactions between Cu/Sn-Ag-(Cu) and Sn-Ag-(Cu)/Ni interfacial reactions were studied during isothermal aging at $150^{\circ}C$ for up to 1000h using Cu(ENIG)/Sn-3.5Ag-(0.7Cu)/Cu(ENIG) sandwich solder joints. A typical scallop-type Cu-Sn intermetallic compound (IMC) layer formed at the upper Sn-Ag/Cu interface after reflowing, whereas a $(Cu,Ni)_6Sn_5$ IMC layer was observed at the Sn-Ag/ENIG interface. The Cu in the $(Cu,Ni)_6Sn_5$ IMC layer formed on the Ni side was sourced from the dissolution of the opposite Cu metal pad or Cu-Sn IMC layer. When the dissolved Cu arrived at the interface of the Ni pad, the $(Cu,Ni)_6Sn_5$ IMC layer formed on the Ni interface, preventing the Ni pad from reacting with the solder. Although a long isothermal aging treatment was performed at $150^{\circ}C$, no Ni was detected in the Cu-Sn IMC layer formed on the Cu side. Compared to the single Sn-Ag/ENIG solder joint, the formation of the $(Cu,Ni)_6Sn_5$ IMC layer of the Cu/sn-Ag/ENIG sandwich joint effectively retarded the Ni consumption from the electroless Ni-P layer.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.121-127
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• 1995

We have analyzed the double insulating layer consisting of anodic oxide and ZnS through TEM experiments. The use of double insulating layer for HgCdTe surface passivation is one of the promising passivation method which has been recently studied deeply and the double insulating layer is formed by the evaporation of ZnS on the top of anodic oxide layer grown in H$_{2}$O$_{2}$ electrolyte. The structure of anodic oxide layer on HgCdTe is amorphous but the structure of oxide layer after the evaporation of ZnS has been changed to micro-crystalline. The interface layer of 150.angs. thickness has been found between ZnS and anodic oxide layer and is estimated to be ZnO layer. The results of analysis on the chemical components of ZnS, the interface layer and anodic oxide layer have showed that Zn has diffused into the anodic oxide layer deeply while Hg has been significantly decreased from HgCdTe bulk to the top of oxide layer. The formation of ZnO interface layer and the change of structure of anodic oxide layer after the evaporation of ZnS are estimated to be defects or to induce the defects which might possibly affect the increase of the positive fixed charges shown in C-V measurements of HgCdTe MIS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.326-329
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• 2002

In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.896-901
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• 2002

The polarization and strain behavior of multilayer ceramic actuators fabricated by tape casting using a PNN-PZT ceramics were investigated in association with electrode size and internal layer number. Spontaneous polarization and strain decreased with increasing electrode size. In addition, the increase of internal layer number brought reduced spontaneous polarization and increased the field-induced strain. Because the actuators structure is designed to stack ceramic layer and electrode layer alternatively, the ceramic-electrode interfaces may act as a resistance to motion of domain wall. To analyze the effect of ceramic-electrode interface, the diffraction intensity ratio of (002) to (200) planes was calculated from X-ray diffraction patterns of samples subjected to a voltage of 200 V. The diffraction intensity ratio of (002) to (200) planes was decreased with increasing electrode size and internal layer number. The diffraction intensity ratio and straining behavior analyses indicate that the Polarization and strain were affected by the amount of 90°domain decreasing with increasing electrode size and internal layer number. Consequently, the change of polarization and displacement with respect to electrode size and layer number is likely to be caused by readiness of the domain wall movement around the interface.