• 한국전자거래학회지
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• 제8권1호
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• pp.1-14
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• 2003

The first edition of ebXML which aims at unimarket was announced at May 1 of 2001. OASIS continues working on the framework of ebXML, and UN/CEFACT does on the contents. In our country, 30 vertical B2B markets are being constructed and most of them adopted ebXML as their main standard. In this situation, we need to make a guideline which can interconnect individual vertical B2B systems. In our study, we propose an architecture for i) Central Registry/Repository for the interconnection of between vertical B2Bs, between ebXML and non-ebXML, and between nations. ii) Information modeling for interconnection. iii) Distributed modeling. We hope our work could be extended by following discussion of academical and industrial researchers.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 22-24 Oct. 1991
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• pp.1149-1154
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• 1991

For a robotic workcell, which consists of multiple robots, several interconnection methods are presented in terms of the processor based architecture. Since few attempts have been made to formulate and analyze multiple robot system(MRS), we turn the knowledge of multiple processor system(MPS) or multiple computer system(MCS) to good account. The performance evaluation is achieved through queueing analysis, the aim being to compare their response time, utilization, probability of service failure under different workload. To verify the validity of the proposed analysis methods, a computer simulation is performed. The results together with comments presented here give some useful guidelines for the selection of an appropriate interconnection method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.647-650
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• 1988

This paper proposes and sketches out a new parallel architecture of transputer-based pyramidal parallel array computer (TPPAC) used to process computationally intensive problems for geometric processing applications such as computer vision, image processing etc. It explores how efficiently the pyramid computer architecture is designed using transputer chips, and poses a new interconnection scheme for TPPAC without using additional transputers.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(3)
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• pp.195-198
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• 2001

Components are abstractions of system level computational entities, connectors are abstractions of component interrelationships. we propose connectors as transferable abstractions of system level component interconnection and inter-operation. Connectors are architectural abstractions of component coordination in the abstract architecture of a system only. Connectors describe a collaboration rationale for component adaptations, which are then modeled in the concrete architecture of a system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.911-915
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• 1987

In this thesis, the architecture and design of IWS(Inter Working System) which interconnects two different networks (PSDN: Packet Switched Data Network, PSTN:Public Switched Telephone Network) are described. IWS provides interconnection services for the compatibility of communication between two networks. IWS consists of network interface protocols, protocol conversion facilities and management facilities.

• 월간 기계설비
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• 통권112호
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• pp.76-80
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• 1999

네트워크는 어떤 공동의 목적을 위해 다수 지점간에 상호 연결된 통신형태를 말한다. 네트워크를 구현하고 표현하기 위한 방법은 여러가지가 있으나 대표적인 방법으로 프로토콜과 토폴로지를 들 수 있을 것이다. 프로토콜은 소프트웨어의 형태이며, 토폴로지는 하드웨어의 형태라고 할 수 있다. 이러한 것들의 집합을 네트워크 아키텍쳐(Network Architecture)라고 하는데, ISO(International Standard Organization)의 OSI(Open System Interconnection) 모델, IBM의 SNA(System Network Architecture)를 기준으로 사용자의 필요와 목적에 따라 다양한 형태로 표현되고 구현된 네트워크 아키텍쳐들이 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• 전기전자학회논문지
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• 제17권2호
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• pp.176-181
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• 2013

This paper presents a CMOS impulse radio ultra-wideband (IR-UWB) receiver implemented using IBM 0.13um CMOS technology for inner/inter-chip wireless interconnection. The IR-UWB receiver is based on the non-coherent architecture which removes the complexity of RF architecture (such as DLL or PLL) and reduces power consumption. The receiver consists of three blocks: a low noise amplifier (LNA) with active balun, a correlator, and a comparator. Simulation results show the die area of the IR-UWB receiver of 0.2mm2, a power gain (S21) of 12.5dB, a noise figure (NF) of 3.05dB, an input return loss (S11) of less than -16.5dB, a conversion gain of 18dB, a NFDSB of 22. The receiver exhibits a third order intercept point (IIP3) of -1.3dBm and consumes 22.9mW of power on the 1.4V power supply.

• Journal of Information Processing Systems
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• 제9권2호
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• pp.301-314
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• 2013

In a parallel processing system, Multi-stage Interconnection Networks (MINs) play a vital role in making the network reliable and cost effective. The MIN is an important piece of architecture for a multiprocessor system, and it has a good impact in the field of communication. Optical Multi-stage Interconnection Networks (OMINs) are the advanced version of MINs. The main problem with OMINs is crosstalk. This paper, presents the (1) Destination Based Modified Omega Network (DBMON) and the (2) Destination Based Scheduling Algorithm (DBSA). DBSA does the scheduling for a source and their corresponding destination address for messages transmission and these scheduled addresses are passed through DBMON. Furthermore, the performance of DBMON is compared with the Crosstalk-Free Modified Omega Network (CFMON). CFMON also minimizes the crosstalk in a minimum number of passes. Results show that DBMON is better than CFMON in terms of the average number of passes and execution time. DBSA can transmit all the messages in only two passes from any source to any destination, through DBMON and without crosstalk. This network is the modified form of the original omega network. Crosstalk minimization is the main objective of the proposed algorithm and proposed network.

• 전자공학회논문지B
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• 제32B권5호
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• pp.720-729
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• 1995

We proposed a XMESH(crossed-mesh) topology as a suitable interconnection for the massively parallel computer architectures, and presented performance analysis of the proposed interconnection topology. Horizontally, the XMESH has the same links as those of the toroidal mesh(TMESH) or toroid, but vertically, it has diagonal cross links instead of the vertical links. It reveals desirable interconnection characteristics for the massively parallel computers as the number of nodes increases, while retaining the same structural advantages of the TMESH such as the symmetric structure, periodic placement of subsystems, and constant degree, which are highly recommended features for VLSI/WSI implementations. Furthermore, n*k XMESH can be easily expanded without increasing the diameter as long as n.leq.k.leq.n+4. Analytical performance evaluations show that the XMESH has a shorter diameter, a shorter mean internode distance, and a higher message completion rate than the TMESH or the diagonal mesh(DMESH). To confirm these results, an optimal self-routing algorithm for the proposed topology is developed and is used to simulate the average delay, the maximum delay, and the throughput in the presence of contention. In all cases, the XMESH is shown to outperform the TMESH and the DMESH regardless of the communication load conditions or the number of nodes of the networks, and can provide an attractive alternative to those networks in implementing massively parallel computers.