• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.83-93
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• 2014

It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.3
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• pp.65-72
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• 2019

HPC(High Performance Computing) is the computing system that connects a number of computing nodes with high performance interconnect network. In the HPC, interconnect network technology is one of the key player to make high performance systems, and mainly, Infiniband or Ethernet are used for interconnect network technology. Nowadays, PCIe interface is main interface within computer system in that host CPU connects high performance peripheral devices through PCIe bridge interface. For connecting between two computing nodes, PCIe Non-Transparent Bridge(NTB) standard can be used, however it basically connects only two hosts with its original standards. To give cost-effective interconnect network interface with PCIe technology, we develop a prototype of interconnect network system with PCIe NTB. In the prototyped system, computing nodes are connected to each other via PCIe NTB interface constructing switchless interconnect network such as ring network. Also, we have implemented prototyped data sharing mechanism on the prototyped interconnect network system. The designed PCIe NTB-based interconnect network system is cost-effective as well as it provides competitive data transferring bandwidth within the interconnect network.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.199-201
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• 2005

USB has arguably become the most successful PC peripheral interconnect ever defined. As appearing UWB, wireless USB (WUSB) emerges very popular technology. However, the distributed Medium Access Control (MAC) does not harmonize with the topology of WUSB. In this paper, we address a novel MAC protocol for conformity with WUSB. The protocol is to handle negotiation on Distributed Reservation Protocol (DRP) including the channel time slot of WUSB.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.38-49
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• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.745-753
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• 2016

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.2
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• pp.232-239
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• 2007

There is an increasing concern to interconnect DG(Distributed Generation) units into a distribution system and operate and maintain the system power quality within a proper level to distribution companies, regional electricity utilities and industrial customers. Recently, this situation makes many experts estimate a next generation of distribution system which is composed of some micro-grids. But the proposed micro-grid is only mentioned as a small grid with some DG units, some power quality compensators, communication and control equipments. In this paper, a topology and an operation/control algorithm of the micro-grid which is able to supply the electricity with high reliability and quality, are proposed.

• Journal of the Korea Society for Simulation
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• v.6 no.2
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• pp.45-57
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• 1997

MAC (media access control) bridge is used to interconnect separate LANs and to relay frames between the BLANs (bridged LANs). Bridge architecture consists of MAC entity, MAC relay entity and bridge protocol entity protocol entity and performs learning, filtering and forwarding functions using filtering database. In this paper, we simulate these functions of bridge and the STP (spanning tree protocol). The STP derives an active topology from an arbitrarily connected BLAN. Our simulation model assumes a BLAN consisted of three bridge forming a closed loop. In order to remove the loop, each bridge process exchanges configruation BPDU (bridge protocol data unit0 with other bridge processes connected to the bridge itself. To simulate the communication between bridges, we implement the IPC (inter-process communication) server using message queues. Our simulation results show that the assumed BLAN contains no closed loop and then there is no alternative route and no unnecessary traffic.

• ETRI Journal
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• v.39 no.5
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• pp.632-642
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• 2017

Digital all-optical parallel computing is an important research direction and spans conventional devices and convergent nano-optics deployments. Optical bus-based interconnects provide interesting aspects such as relative information communication speed-up or slow-down between optical signals. This aspect is harnessed in the newly proposed All-Optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) model. However, the physical realization of such communication interconnects needs to be considered. This paper considers spatial layouts of processing elements along with the optical bus light paths that are necessary to realize the corresponding interconnection requirements. A metric in terms of the degree of required physical constraint is developed to characterize the variety of possible solutions. Simple algorithms that determine spatial layouts are given. It is shown that certain communication interconnection structures have associated intrinsic topologies.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.22-33
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• 1999

In this paper, we propose a new multi-way circuit partitioning system that partition large circuits to progrmmable circuit board which consist of FPGAs and interconnect components. Here the routing topology among the chips are predetermined and the number of available interconnections are fixed. Since the given constraints are difficult to be satisfied by the previous partition method, we suggest a new multi-way partition method by target restriction that considers all the constraints for the given board. To speed up, we construct a multi-level cluster tree for hierarchical partitioning. Experimental results for several benchmarks show that the our partition method partition them by satisfying all the given constraints and it used up to 10 % fewer interconnections among the chips than the previous K-way partition method.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.10
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• pp.65-72
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• 2015

Recently, LED light has been increasingly adopted for vehicles in both domestic and foreign automotive markets, while a variety of LED lights have been developed to be used particularly for headlamps. In this paper, we propose an H-type resonant snubber circuit topology for high efficiency of vehicle LDM (LED Driver Module) and realized LDM functions for vehicle headlamp by designing high-efficiency convertors. In addition, this study reduced the financial burden by configuring the system to control the whole with micom except for the use of individual dedicated chips to drive LED for high and low beam. In order to verify the validity of the proposed H-type resonant snubber capable of soft switching, simulations were performed using PSIM. As a result, the validity was experimentally verified by creating a prototype. Moreover, in order to actually attach the headlamp, the performance of the proposed convertor was confirmed by designing LDM to the limited size. Communications between the headlamp and higher controller were realized using LIN(Local Interconnect Network).