• Journal of electromagnetic engineering and science
• /
• v.6 no.1
• /
• pp.18-23
• /
• 2006

In this paper, we demonstrate a fully integrated X-band image rejection down converter, which was developed using InGaP/GaAs HBT MMIC technology, consists of two single-balanced mixers, a differential buffer amplifier, a differential YCO, an LO quadratue generator, a three-stage polyphase filter, and a differential intermediate frequency(IF) amplifier. The X-band image rejection downconverter yields an image rejection ratio of over 25 dB, a conversion gain of over 2.5 dB, and an output-referred 1-dB compression power$(P_{1dB,OUT})$ of - 10 dBm. This downconverter achieves broadband image rejection characteristics over a frequency range of 1.1 GHz with a current consumption of 60 mA from a 3-V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.12
• /
• pp.53-60
• /
• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• The KIPS Transactions:PartA
• /
• v.11A no.2
• /
• pp.195-202
• /
• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.