• Title/Summary/Keyword: Integrated Receiver

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Development of 3D CSGNSS/DR Integrated System for Precise Ground-Vehicle Trajectory Estimation (고정밀 차량 궤적 추정을 위한 3 차원 CSGNSS/DR 융합 시스템 개발)

  • Yoo, Sang-Hoon;Lim, Jeong-Min;Jeon, Jong-Hwa;Sung, Tae-Kyung
    • Journal of Institute of Control, Robotics and Systems
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    • v.22 no.11
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    • pp.967-976
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    • 2016
  • This paper presents a 3D carrier-smoothed GNSS/DR (Global Navigation Satellite System/Dead Reckoning) integrated system for precise ground-vehicle trajectory estimation. For precise DR navigation on sloping roads, the AHRS (Attitude Heading Reference System) methodology is employed. By combining the integrated carrier phase of GNSS and DR sensor measurements, a vehicle trajectory with an accuracy of less than 20cm is obtained even when cycle slip or change of visibility occur. In order to supplement the weak GNSS environment with DR successfully, the DR sensor is precisely compensated for using GNSS Doppler measurements when GNSS visibility is good. By integrating a multi-GNSS receiver with low-cost IMU, a precise 3D navigation system for land vehicles is proposed in this paper. For real-time implementation, a decoupled Kalman filter is employed in the integrated system. Through field experiments, the performance of the proposed system is verified in various road environments, including sloping roads, good-visibility areas, high multi-path areas, and under-ground parking areas.

A 900 MHz RFID Receiver with an Integrated Digital Data Slicer (디지털 데이터 슬라이서가 집적된 900 MHz 대역의 RFID 수신단)

  • Cho, Younga;Kim, Dong-Hyun;Kim, Namhyung;Rieh, Jae-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.1
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    • pp.63-70
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    • 2015
  • In this paper, a receiver has been developed in a $0.11-{\mu}m$ CMOS technology for 900 MHz RFID communication system applications. The receiver is composed of an envelope detector, a low-pass-filter, a comparator, D flip-flops, as well as an oscillator to provide the clock for digital blocks. The receiver is designed for low power consumption, which would be suitable for passive RFID tags. In this circuit, a digital data slicer was employed instead of the conventional analog data slicer in order to reduce the power consumption. The clock frequency is 1.68 MHz and the circuit operates with a power consumption as small as $5{\mu}W$. The chip size is $325{\mu}m{\times}290{\mu}m$ excluding the probing pads.

A $0.5{\mu}m$ CMOS FM Radio Receiver For Zero-Crossing Demodulator (Zero-Crossing 복조기를 위한 $0.5{\mu}m$ CMOS FM 라디오 수신기)

  • Kim, Sung-Woong;Kim, Young-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.100-105
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    • 2010
  • In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.

Study on INS/GPS Sensor Fusion for Agricultural Vehicle Navigation System (농업기계 내비게이션을 위한 INS/GPS 통합 연구)

  • Noh, Kwang-Mo;Park, Jun-Gul;Chang, Young-Chang
    • Journal of Biosystems Engineering
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    • v.33 no.6
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    • pp.423-429
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    • 2008
  • This study was performed to investigate the effects of inertial navigation system (INS) / global positioning system (GPS) sensor fusion for agricultural vehicle navigation. An extended Kalman filter algorithm was adopted for INS/GPS sensor fusion in an integrated mode, and the vehicle dynamic model was used instead of the navigation state error model. The INS/GPS system was consisted of a low-cost gyroscope, an odometer and a GPS receiver, and its performance was tested through computer simulations. When measurement noises of GPS receiver were 10, 1.0, 0.5, and 0.2 m ($1{\sigma}$), RMS position and heading errors of INS/GPS system at 5 m/s straight path were remarkably reduced with 10%, 35%, 40%, and 60% of those obtained from the GPS receiver, respectively. The decrease of position and heading errors by using INS/GPS rather than stand-alone GPS can provide more stable steering of agricultural equipments. Therefore, the low-cost INS/GPS system using the extended Kalman filter algorithm may enable the self-autonomous navigation to meet required performance like stable steering or more less position errors even in slow-speed operation.

An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications

  • Rastegar, Habib;Ryu, Jee-Youl
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.5
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    • pp.595-604
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    • 2016
  • Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

A Study on the Implementation of Integrated Management System for CATV Network (CATV망 관리를 위한 통합관리 시스템 구현 사례 연구)

  • 곽윤식
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.5
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    • pp.1082-1088
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    • 2003
  • This study is about the development of a system related to the CATV network. It intends to develop an automatically centralized Headend system and a distributive system to remove the ineffectiveness of the established manual system. To achieve this goal, we took a put of bandwidth, which is not used for the transmission of video signals in the established frequency bandwidth, and used it for the transmission and receiver of controlling signals. By this way we could design a system of transmission and receiver and a automatic distributive system. We developed an information management system for the 9600bps CATV using RS-232 of forward/backward communication and backward communication. Based on window, It consist of ID generation, transmitter/receiver, control and backup part.

A PLC-Based Optical Sub-assembly of Triplexer Using TFF-Attached WDM and PD Carriers

  • Han, Young-Tak;Park, Yoon-Jung;Park, Sang-Ho;Shin, Jang-Uk;Kim, Duk-Jun;Park, Chul-Hee;Park, Sung-Woong;Kwon, Yoon-Koo;Lee, Deug-Ju;Hwang, Wol-Yon;Sung, Hee-Kyung
    • ETRI Journal
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    • v.28 no.1
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    • pp.103-106
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    • 2006
  • We have fabricated a planar lightwave circuit (PLC) hybrid-integrated optical sub-assembly of a triplexer using a thin film filter (TFF)-attached wavelength division multiplexer (WDM) and photodiode (PD) carriers. Two types of TFFs were attached to a diced side of a silica-terraced PLC platform, and the PD carriers with a $45^{\circ}$ mirror on which pin-PDs were bonded were assembled with the platform. A clear transmitter eye-pattern and minimum receiver sensitivity of -24.5 dBm were obtained under 1.25 Gb/s operation for digital applications, and a second-order inter-modulation distortion (IMD2) of -70 dBc was achieved for an analog receiver.

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Development on the Sub-Cooled Hybrid Condenser in Automotive Air-Conditioning System (자동차 냉방시스템에서 건조기 일체형 응축기 개발)

  • 김경훈;장주섭;박종일
    • Transactions of the Korean Society of Automotive Engineers
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    • v.11 no.5
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    • pp.70-76
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    • 2003
  • An experimental study was performed to understand the heat transfer and fluid dynamic characteristics of Sub-Cooled Hybrid Condenser (SCHC), which conventional condenser and receiver dryer are integrated into. SCHC also employs a sub-cooled refrigerant passages at the end of the condenser in order to supply perfect liquid refrigerant to the expansion unit. Throughout the present study, it was found that the developed SCHC increases in the degree of sub-cooling by 10~100% compared to conventional condenser. The excessive sub-cooling has improved the cooling performance by 10%, and that leads reduction in evaporator outlet air temperature by $1.5^{\circ}C$. Also found through the study is that the refrigerant pressure drop across SCHC is fairly increased due to insertion of the desiccant cartridge in the receiver tank which is composed of zeolite, filter and supporter plate.

Design Methodology of MMIC for X-Band DBS Receiver Front ends using GaAs (GaAs를 이용한 X-Band용 DBS 수신기 전단부의 MMIC 설계)

  • Cho, Seung-Ki;Rhee, Jin-Koo;Kim, Sang-Myung;Cho, Gwang-Rae;Yoon, Hyun-Bo
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1564-1568
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    • 1987
  • A design methodology for front ends of a Direct Broadcasting satellite (DBS) Receiver for X-band was reported by utilizing Monolithic Microwave Integrated Circuits (MMIC) technology. The frequency converter including a three-stage low-noise amplifier, a image frequency rejection filter, and a mixer and buffer amplifier was designed by a Home-made CAD program. The results of computer simulation using the CAD program showed that overall gain was over 36.63dB, and noise figure below 2.55dB, respectively.

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Development of low power GPS receiver

  • Kim, Il-Kyu;Lee, Jae-Ho;Seo, Hung-Serk;Park, Chan-Sik;Lee, Sang-Jeong
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.114.6-114
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    • 2001
  • According to expansion of wireless communication system and mobile device, interest has been growing in personal navigation system integrated with wireless system. In portable consumer electronics, such as cellular phones, GPS and PDA, one of major design factors is the power consumption. Solutions of reducing the power dissipation are low voltage, low system clock power management and so on. This paper develops a GPS receiver based on the advanced power management algorithm that achieves very low average power consumption. Both RF and DSP chips are powered down and reactivated only when the position fixing is required. In order to run, the developed includes the RTC calibration function and the fast reacquisition function using XMC (eXtended Multiple Correlator) ...

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