• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.124-130
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• 2013

In this paper, a new motion estimation algorithm with low-computational complexity is proposed to improve the performance of H.264/AVC. The proposed architecture uses the directions of the median motion vector which is computed by the motion vectors of the three neighbor macroblocks in Integer Motion Estimation. By using the directions of the vector, the proposed architecture has a single computational level instead of multi-computational levels in Integer Motion Estimation. The proposed motion estimation is synthesized using the TSMC 0.18um standard cell library. The synthesis result shows that the gate count is about 217.92K at 166MHz and it was improved about 69% compared with previous one.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.11b
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• pp.1006-1009
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• 2003

In a motion estimation method for use in encoding a moving picture, a full-pixel motion vector is estimated by stochastically sampling a pixel to be processed in a predetermined-sized block of a previous frame or a next frame as a reference frame for each of a plurality of equal-sized blocks in a current frame. Then, a half-pixel motion vector is estimated based on the full-pixel motion vector. Accordingly, both the calculation amount and the calculation time required for the motion estimation are effectively reduced. Further, it can be prevented that the hardware becomes complicated. .

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.669-678
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• 2012

In this paper, we propose an efficient fast integer-pel motion estimation for H.264/AVC using local statistics of local motion vectors. Using neighboring motion vectors, we define a new statistical property that is used to determine a mode of motion search range of current block. In addition, an adaptive motion search range compensated method that is based on cumulative statistics of previous coded blocks is addressed to solve the problem of the statistical motion search range decision method. Experimental results show that proposed algorithm has the capability to reduce the computational cost over the other methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.48-54
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• 2010

This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at R1L and verified its operation on FPGA board. The circuit synthesized by using l30nm CMOS standard cell library processes 139.8 1080HD ($1,920{\times}1,088$) image frames per second and supports up to H.264 level 5.1.

• Journal of Broadcast Engineering
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• v.19 no.5
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• pp.699-712
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• 2014

In this paper, we propose a new Adaptive Search Range (ASR) decision algorithm for accelerating GPU-based Integer-pel Motion Estimation (IME) of High Efficiency Video Coding (HEVC). For deciding the ASR, we classify a frame into two models using Motion Vector Differences (MVDs) then adaptively decide the search ranges of each model. In order to apply the proposed algorithm to the GPU-based ME process, starting points of the ME are decided using only temporal Motion Vectors (MVs). The CPU decides the ASR as well as the starting points and transfers them to the GPU. Then, the GPU performs the integer-pel ME. The proposed algorithm reduces the total encoding time by 37.9% with BD-rate increase of 1.1% and yields 951.2 times faster ME against the CPU-based anchor. In addition, the proposed algorithm achieves the time reduction of 57.5% in the ME running time with the negligible coding loss of 0.6%, compared with the simple GPU-based ME without ASR decision.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.87-90
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• 2003

This paper presents a variable block size motion estimation (ME) algorithm and hardware architectures dedicated to H.264/AVC. Proposed ME architecture can achieve real-time processing for 720$\times$480@30Hz with search range of [-64, +63] in the horizontal and [-32, +31] in the vertical direction at integer-pel accuracy and upto 7 reference frames at the operating frequency of 54MHz.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.9
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• pp.4587-4605
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• 2019

High Efficiency Video Coding (HEVC) suffers from high computational complexity due to its quad-tree structure in motion estimation (ME). This paper exposes an adaptive search range decision algorithm for accelerating HEVC integer-pel ME on GPU which estimates the optimal search range (SR) using a MAP (Maximum A Posteriori) estimator. There are three main contributions; First, we define the motion feature as the standard deviation of motion vector difference values in a CTU. Second, a MAP estimator is proposed, which theoretically estimates the motion feature of the current CTU using the motion feature of a temporally adjacent CTU and its SR without any data dependency. Thus, the SR for the current CTU is parallelly determined. Finally, the values of the prior distribution and the likelihood for each discretized motion feature are computed in advance and stored at a look-up table to further save the computational complexity. Experimental results show in conventional HEVC test sequences that the proposed algorithm can achieves high average time reductions without any subjective quality loss as well as with little BD-bitrate increase.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.21-27
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• 2019

The video compression standard required a processing technique for a high resoluion image and increased the coding size to increase the resolution of the image. Accurate motion estimation and increased coding size provide high accuracy and compression rate, but there is a problem of increased computational complexity. In this paper, we use DCT - based motion estimation in the frequency domain to reduce complexity. However, we found that the DCT and quantization process used in a general video encoder are applied to the frequency domain encoder, resulting in problems caused by the scaling process. Therfore, in this paper, we extract the scaling matrix that can be applied in the DCT step and resolve the, and improve the performance of motion estimation using increased coding size.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.53-60
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• 2009

Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.6
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• pp.209-220
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• 2004

The main feature of H.264 standard against conventional video standards is the high coding efficiency and the network friendliness. In spite of these outstanding features, it is not easy to implement H.264 codec as a real-time system due to its high requirement of memory bandwidth and intensive computation. Although the variable block size motion compensation using multiple reference frames is one of the key coding tools to bring about its main performance gain, it demands substantial computational complexity due to SAD (Sum of Absolute Difference) calculation among all possible combinations of coding modes to find the best motion vector. For speedup of motion estimation process, therefore, this paper proposes fast algorithms for both integer-pel and fractional-pel motion search. Since many conventional fast integer-pel motion estimation algorithms are not suitable for H.264 having variable motion block sizes, we propose the motion field adaptive search using the hierarchical block structure based on the diamond search applicable to variable motion block sizes. Besides, we also propose fast fractional-pel motion search using small diamond search centered by predictive motion vector based on statistical characteristic of motion vector.