• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.141-151
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• 1994

this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.4
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• pp.292-298
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• 2017

The complexity of image compression algorithms has increased in order to improve image compression efficiency. One way to resolve high computational complexity is parallel processing. However, entropy coding, which is lossless compression, does not fit into the parallel processing form because of the correlation between consecutive symbols. This paper proposes a new application-specific instruction set processor (ASIP) platform by adding new context-adaptive binary arithmetic coding (CABAC) instructions to the existing platform to quickly process a variety of entropy coding. The newly added instructions work without conflicts with all other existing instructions of the platform, providing the flexibility to handle many coding standards with fast processing speeds. CABAC software is implemented for High Efficiency Video Coding (HEVC) and the performance of the proposed ASIP platform was verified with a field programmable gate array simulation.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.32.1-32
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• 2001

Up to now, many studies on human-machine interface with voice systems have been reported. However, in these systems, precise instructions are necessary for a robot to execute given tasks successfully. In order to make a robot friendly, more ambiguous instructions with some kinds of degree adverbs (, e.g., "move it a little", "lift it more" and so on, ) will be preferable. Therefore, we analyze the relationship between ambiguous instructions and the characteristics of instructed human motion in positioning task to design human friendly interface systems. Several experimental results show that adverbial expressions are mainly divided into three clusters corresponding to the displacement, and that instructors and perators have several differences in distance sense each other.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.184-187
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• 2000

A network is an important portion of communications in these days. Because of many inconveniences of a wired-network, wireless solutions have been studied for many years. One of the results of those efforts is IEEE 802.11, wireless LAN. This paper briefly summarizes wireless LAN and specially focuses on the design of a network processor for the wireless LAN system. The processor has 16-bit instruction set suitably selected for network processing and low-power consumption. It is implemented and verified with a wireless LAN system model. The wireless LAN system is modeled in RTL excluding the RF module. The processor can be used in many wireless systems as a controller and utilized as a test module for the research of low-power schemes.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.867-870
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• 2003

본 논문은 멀티미디어 데이터 처리를 위한 효율적인 RISC 프로세서 유닛의 설계를 목표로 Vector 프로세서의 SIMD(Single Instruction Multiple Data) 개념을 바탕으로 고정된 연산기 데이터 비트 수에 비해 상대적으로 작은 비트수의 데이터 연산의 부분 병렬화를 통하여 멀티미디어 데이터 연산의 기본이 되는 곱셈누적(MAC : Multiply and Accumulate) 연산의 성능을 향상 시킨다. 또한 기존의 MMX나 VIS 등과 같은 범용 프로세서들의 부분 병렬화를 위해 전 처리 과정의 필요충분조건인 데이터의 연속성을 위해 서로 다른 길이의 데이터 흑은 비트 수가 작은 멀티미디어의 데이터를 하나의 데이터로 재처리 하는 재정렬 혹은 Packing/Unpacking 과정이 성능 전체적인 성능 저하에 작용하게 되므로 본 논문에서는 기존의 프로세서의 연산기 구조를 재이용하여 병렬 곱셈을 위한 연산기 구조를 구현하고 이를 위한 데이터 정렬 연산 구조를 제안한다.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.257-260
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• 1999

We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.

• English Language & Literature Teaching
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• v.18 no.2
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• pp.1-20
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• 2012

This study aims to propose using English reading strategies to enhance Intercultural Communicative Competence (ICC) for EFL learners. The study recruited college-level participants who were enrolled in a general English reading course (N=30) and administrated the surveys with a Repeated Measures Design (RMD). In the survey, an intercultural sensitivity scale and metacognitive reading strategies inventory were conducted for comparison. During the instruction, participants were asked to use the R.I.D.E.R. (i.e. Read, Image, Describe, Evaluate, and Repeat) strategy for visualization of text, which is aimed at facilitating the use of metacognitive reading strategies. In the results, participants showed a statistically significant increase both in the intercultural sensitivity level and the use of metacognitive reading strategies after the practice of R.I.D.E.R for one semester. Further analysis was appended to the results by the correlation and regression analysis, and proposed that participants benefit their development of intercultural sensitivity from the use of metacognitive reading strategies. Therefore, the study suggests that implementing metacognitive reading strategies facilitates college EFL readers to increase their cultural sensitivity, which empowers ICC through English reading (176words).

• International journal of advanced smart convergence
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• v.5 no.2
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• pp.8-17
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• 2016

Scratch-based programming has come to be known as an effective programming tool because of its graphic instruction modules, which are designed to be assembled like the famous LEGO building blocks. These building block-like structures allow users to more easily program applications without using other more difficult programming languages such as C or Java, which are text-based. Therefore, it poses a good opportunity for application in educational settings, especially in primary schools. This paper presents an effective approach to developing an educational robot for use in elementary schools. Furthermore, we present the method for scratch programming based on the external modules need for the implementation of robot motion. Lastly, we design a systematic curriculum, titled "Play with a Robot," and propose guidelines to using the educational programming language Scratch.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.27-30
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• 2003

The recent technology developments introduce new difficulties into the test process by the increased complexity of the chip. Most widely used method for testing high complexity and embedded systems is built-in self-test(BIST). In this paper, we describe 5-stage pipeline system as circuit under testing(CUT) and proposed a BIST scheme for the hazard detection unit of the pipeline system. The proposed BIST scheme can generate sequential instruction sets by pseudo-random pattern generator that can detect all hazard issues and compare the expected hazard signals with those of the pipelined system. Although BIST schemes require additional area in the system, it proves to provide a low-cost test solution and significantly reduce the test time.

• Proceeding of Spring/Autumn Annual Conference of KHA
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• 2003.11a
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• pp.173-179
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• 2003

This study analyzes the problems, which the residential inner area has, and proposes systematic and gradual progressing improvement plan for the residential environment in the inner area. Also, planning instruction is proposed through the case study of parcel·jointed complex housing. This study can be concluded as below: (1) Improvement plans sub-divided into promoting districts and inducing districts of the residential inner area are proposed. (2) Necessity for construction of streets is proposed in order to compensate existing problems in sites. (3) Necessity of complex housings is proposed fur roadsides of household unit or small-sized annexation of parcel. (4) Collecting design examples and existing literatures, the planning guideline for jointed parcel complex housing is proposed based on the established relation with a whole surface of streets, formation and distribution of purposes and increased role of exterior space.