• Journal of Power Electronics
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• 제2권3호
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• pp.162-170
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• 2002

Voltage sag detection algorithm for voltage sag corrector is proposed in this paper. To quantify the standard of voltage unbalance under the faulted conditions, the 3-phase unbalanced voltages are decomposed into two balanced 3-phase symmetrical components of the positive and negative sequence voltages, which is defined by the magnitude factor (MF) and unbalance factor (UF). It is analyzed that MWF and UF values are given as the dc constant values even though under the voltage unbalance condition. This paper also proposes the control scheme of the instantaneous voltage sag corrector based on this detection algorithm. The validity of the proposed algorithm is verified through the EMTDC simulation and experiments.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제50권1호
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• pp.15-22
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• 2001

In this paper, a VSC(Voltage Sag Corrector) is discussed for the purpose of power quality enhancement. A fast detecting technique of voltage sag is accomplished through the detection of instantaneous value on synchronous reference frame. A robust characteristic against the noise is available by inserting the first order low pass filter in the detection circuit. The formula and the filter design process is described properly with the mathematical equations. Because the VSC system supply the active power to load, it is required to design the proper size of the energy storage system, In this paper, the capacitor bank is used as an energy storage system, and the size of the capacitor is designed from the point of view of input/output energy as the output power rating and the amplitude and duration time of the voltage sag. The simulation is accomplished by PSCAD/EMTDC.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 전력전자학술대회 논문집
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• pp.172-176
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• 2001

In this paper, a new detection algorithm of faulted voltages under the unbalanced condition and a control algorithm of the instantaneous voltage sag corrector (IVSC) are proposed. To quantify the unbalance under fault conditions, the voltages are decomposed into two balanced three-phase systems using the symmetrical components of positive and negative sequence voltages, which is defined by magnitude factor (MF) and unbalance factor (UF). New control algorithm based on MF and UF values for instantaneous voltage compensation are proposed and verified through the PSCAD/EMTDC simulation and experimental results.

• 전기학회논문지P
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• 제55권1호
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• pp.21-25
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• 2006

This paper describes the novel control techniques design of VSC(Voltage Sag Corrector) for the purpose of power line quality enhancement. A fast detecting technique of voltage sag is implemented through the detection of instantaneous value on synchronous rotating do-reference frame. The first order digital filter is added in the detection algorithm to protect the insensitive characteristics against the noise. The relationship between the total detection time and cut-off frequency of the filter is described. The size of the capacitor bank used as the energy storage element is designed from the point of view of input/output energy with circuit analysis. Finally, the validity of the proposed scheme is proven through the simulated results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.502-507
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• 2001

This paper proposes a novel detection algorithm of faulted voltages under the unbalanced condition. To quantify the standard of unbalance under the faulted conditions, the 3-phase unbalanced voltages are decomposed into two balanced 3-phase symmetrical components of the positive and negative sequence voltages, which is defined by the magnitude factor (MF) and unbalance factor (MF). It is analyzed that MF and UF values are given as the dc constant values even though unbalance condition. This paper also proposes the control scheme of the instantaneous voltage sag corrector based on this detection algorithm. The validity of the proposed algorithm is verified through the EMTDC simulation and experiments.

• 조명전기설비학회논문지
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• 제20권3호
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• pp.6-11
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• 2006

본 논문은 전력품질 향상을 목적으로 VSC의 새로운 제어 기법의 디자인에 대하여 기술하였다. 전압강하의 빠른 검출 기술은 동기 회전 d q-기준축에서 순시값의 검출을 통해서 구현되었다. 1차 디지털 필터는 노이즈에 대하여 둔감한 특성을 막을 수 있는 검출 알고리즘을 부가하였다. 필터의 전체 검출과 컷오프 주파수 사이에서 관계에 대하여 기술하였다. 에너지 저장 요소로서 사용되는 캐패시터 뱅크의 사이즈는 회로 해석으로서 입 출력 에너지의 관점에서 디자인 되었다. 마지막으로, 제안된 기법의 유효성은 모의실험을 통하여 증명되었다.

• 전력전자학회논문지
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• 제6권2호
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• pp.173-179
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• 2001

본 논문은 배전계통의 전력품질 개선을 위한 순시 전압강하 보상기의 제어 알고리즘에 대한 연구를 수행하였다. 특별히 순시적인 전압강하의 원인중 가장 대표적인 1선 지락사고 시에 발생하는 불평형과 비대칭 문제를 해석하기 위하여 새로운 대칭성분 검출 기법을 제안하였다. 제안되 방법은 간단한 연산만을 사용하며, 전압보상을 위한 대칭성분의 제어 기준값이 별도의 위상검출 과정을 거치지 않고도 직류 값으로 표현되도록 하였다. 그리고 기준전압의 발생 시에 IEC에서 규정하고 있는 UF와 MF를 사용하도록 하였다. 제안된 제어기법을 사용하면 보상장치는 매우 빠른 응답특성을 가지고 보상된 전압 파형의 총고조파왜형률(THD)도 매우 낮게 된다. 마지막으로 EMTDC 시뮬레이션과 실험을 통하여 제안된 방법의 타당성을 입증하였다.