• 한국자동차공학회논문집
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• 제16권6호
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• pp.26-32
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• 2008

This research presents a simulation for the fuel economy of parallel diesel hybrid vehicle. Diesel engines compared to gasoline engines have the advantages of higher fuel economy and lower $CO_2$ emission. One of the most ways to meet future fuel economy and emissions regulation is to combine diesel engine technology with a hybrid electric vehicle. The simulation of HEV is growing need for rapid analysis of the many configurations and component options. WAVE, a one-dimensional engine analysis tool, was used to a 2.7L diesel engine. ADVISOR, designed for rapid analysis of the performance and fuel economy of vehicle models, was used to conventional and hybrid electric vehicle by the use of output file from WAVE as the input engine data file for ADVISOR. A parallel diesel HEV is at least $19.7{\sim}36%$ higher fuel economy and improved acceleration ability compared to a conventional diesel vehicle. The energy loss of the parallel diesel HEV is $23{\sim}38%$ less than the conventional vehicle using regeneration.

• Journal of Power Electronics
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• 제15권2호
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• pp.327-337
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• 2015

This study discusses the design of a parallel-operated DC-DC single-ended primary-inductor converter (SEPIC) for low-voltage application and current sharing with a constant output voltage. A coupled inductor is used for parallel-connected SEPIC topology. Generally, two separate inductors require different ripple currents, but a coupled inductor has the advantage of using the same ripple current. Furthermore, tightly coupled inductors require only half of the ripple current that separate inductors use. In this proposed work, tightly coupled inductors are used. These produce an output that is more efficient than that from separate inductors. Two SEPICs are also connected in parallel using the coupled inductors with a single common controller. An analog control circuit is designed to generate pulse width modulation (PWM) signals and to fulfill the closed-loop control function. A stable output current-sharing strategy is proposed in this system. An experimental setup is developed for a 18.5 V, 60 W parallel SEPIC (PSEPIC) converter, and the results are verified. Results indicate that the PSEPIC provides good response for the variation of input voltage and sudden change in load.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.789-792
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• 2005

In this paper, we propose a method that applies pipeline architecture to parallel CRC circuits. We developed a logic partitioning algorithm for applying pipeline architecture. Our algorithm can be used for the polynomial and the input data width, both of arbitrary length and minimize the logic level. Design experiments show the superiority of our approach in reducing the delay in comparison with previous works.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.106-109
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• 1999

A single-switched series element for series-parallel compensated UPS is proposed. The proposed series element can handle only unidirectional power and the input voltage must be higher than the output voltage. But it is very useful when DC-link voltage is low and isolation transformer is need for output stage since only one active switch is used.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.122-125
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• 1999

The AC-to-DC single-phase PWM rectifier for traction applications using high power semiconductor, IGCT is made and tested. Parallel operation of two PWM converter is adopted for increasing capacity of converters. For reducing harmonics, the harmonic content is eliminated by the phase shift between two converters switching phase. The output voltage control is achieved by interns calculation without detecting the input current. The part of PLL used for controlling power factor is simply implemented by software.

• 대한전자공학회논문지
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• 제27권9호
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• pp.1344-1350
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• 1990

A design method of ultra-broadband microwave amplifier is presented. A lossy network is represented as the combination of a serial impedance component and a parallel admittance component, and the realizable ranges of the gain and the reflection coefficients are derived with the components connected to the input, output or interstage network. The matching network has been designed by using the serial and parallel immittance loci which have the constant gain or reflection coefficients within the realizable ranges. Using the proposed method, deisgn examples of ultra-broadband amplifiers operating from dc to 12GHz frequency range are presented.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 D
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• pp.2936-2938
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• 2000

Fuzzy controllers have a problem which is the number of rules increase exponentially, when the number of input and output increase. It makes hard to decide the rules and membership functions. In this paper, we suggest parallel fuzzy controllers, and the method to decrease the number of rules. The excellent performance of these methods are confirmed through simulations.

• 전기의세계
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• 제31권3호
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• pp.226-234
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• 1982

DC choppers are usually used to control the DC motor by varying the average value of DC input voltage to the DC motors. In this paper, a chopper circuit is suggested and reconstructed by replacing the free-wheeling diode with the parallel capacitor in the conventional ones. It is demonstrated that this chopper circuit with capacitor can reduce the ripples of the output voltage and current in contrast to those of the chopper with diode, and it can be controlled the output waveforms smoothly at high power demand.

• 한국정보처리학회논문지
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• 제6권4호
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• pp.901-915
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• 1999

분산 메모리 병렬 컴퓨터의 성능을 충분히 활용하고 프로그래밍의 난이도아 기종간 프로그램의 호환성을 해결하기 위하여 시스템 독립적이고 쉽게 프로그래밍 할 수 있는 데이터 병렬 언어에 대한 연구가 최근에 활발히 진행되고 있다. 대표적인 데이터 병렬 언어인 HPF 컴파일러는 사용자가 정의한 정보를 이용하여 데이터와 연산을 프로세서에 분할하여 할당하고, 메시지 패싱을 생성하는 기능을 제공함으로써 프로그램 작성자에게 전역 주소 공간을 이용하여 병렬 프로그램을 쉽게 개발 할 수 있는 기반을 제공한다. 본 논문에서는 데이터 종속성 분석, 데이터 및 연산 분할과 메시지 패싱 코드 생성의 4단계를 통하여, HPf 입력 프로그램을 MPI 메시지 패싱 코드가 삽입된 SPMD 프로그램으로 변환하는 HPF 병렬 프로그래밍 언어 변환기인 PPTran을 구현하고 그 성능을 검증한다.

• 전기전자학회논문지
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• 제8권2호
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• pp.172-180
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• 2004

본 논문에서는 다치 논리회로를 구현하는 방식 중 전압 모드 방식에서 $neuron(\nu)MOS$ Down-literal circuit(DLC)의 다중 문턱전압 성질을 이용하여 유한체 $GF(3^m)$상에서 모든 항의 계수가 존재하는 기약 다항식에 대한 승산 알고리즘(AOTP)을 적용한 병렬 입-출력 모듈 구조의 승산기의 회로를 제안하였다. 3치 입력 신호가 인가되는 승산기는 뉴런모스 DLC를 이용하여 모듈화되고, 모듈에서 변환된 3치 입력 신호를 Pass 게이트를 통해서 선택하는 방식으로 승산 및 가산 게이트를 구현하였다. 설계된 승산기의 회로들은 +3V의 단일 공급 전원에서 $0.35{\mu}m$ N-well double-poly four-metal CMOS 공정의 모델 파라미터를 사용하여 모의실험이 수행되었다. 모의실험 결과를 통하여 승산기는 샘플링 레이트가 3MHz, 소비전력은 $4{\mu}W$, 출력은 ${\pm}0.1V$이내의 전압레벨을 유지하는 것을 알 수 있다.