• Title/Summary/Keyword: Input limiter

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Fabrication and Characteristic Test of Conduction-Cooled Brass Current Leads for a 22.9kV/630A Resistive Superconducting Fault Current Limiter System (22.9kV/630A 저항형 초전도 한류기용 전도-냉각 황동 전류인입선 제작 및 특성 실험)

  • Song, J.B.;Kim, J.H.;Kwon, N.Y.;Kim, Y.W.;Kim, H.M.;Sim, J.;Lee, B.W.;Kim, H.R.;Hyun, O.B.;Lee, H.G.
    • Progress in Superconductivity and Cryogenics
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    • v.9 no.3
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    • pp.46-51
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    • 2007
  • The 22.9kV/630A superconducting fault current limiter (SFCL) is developed by the KEPRI-LSIS collaboration group. This resistive SFCL uses three pairs of conduction-cooled current leads. When the SFCL system is in the fault mode. the current flows 20 times more than the steady state. Therefore. it is important that the current lead is designed to have the thermal stability in order to minimize the heat input of the cold-end. This paper presents the design and performance results of a pair of conduction-cooled brass current leads considering both cases that the SFCL system operates at the steady state and the fault current.

PID Controller and Derivative-feedback Gain Design of the Direct-drive Servo Valve Using the Root Locus and Manual Tuning (근궤적과 수동 조정에 의한 직접 구동형 서보밸브의 PID 제어기 및 미분피드백 이득 설계)

  • Lee, Seong Rae
    • Journal of Drive and Control
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    • v.13 no.3
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    • pp.15-23
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    • 2016
  • The direct-drive servo valve(DDV) is a kind of one-stage valve because the main spool valve is directly driven by the dc motor. Since the DDV structure is simple, it is less expensive, more reliable, and offers a reduced internal leakage and a reduced sensitivity to fluid contamination. The control system of the DDV is highly nonlinear due to a current limiter, a voltage limiter, and the flow-force effect on the spool motion. The shape of the step response of the DDV-control system varies considerably according to the magnitudes of the step input and the load pressure. The system-design requirements mean that the overshoots should be less than 20%, and the errors at 0.02s should be less than 2%, regardless of the reference-step input sizes of 1V and 5V and the load-pressure magnitudes of 0MPa and 20.7MPa. To satisfy the system-design requirements, the PID-controller parameters of $K_c$, $T_i$ and $T_d$, and the derivative-feedback gain of $K_{der}$ are designed using the root locus and manual tuning.

S-Band Low Noise Amplifier Based on GaN HEMT for High Input Power Robustness (고입력 내성을 위한 GaN HEMT 기반 S-대역 저잡음 증폭기)

  • Kim, Hong-Hee;Kim, Sang-Hoon;Choi, Jin-Joo;Choi, Gil-Wong;Kim, Hyoung-Joo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.2
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    • pp.165-170
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    • 2015
  • In this paper, we present design and measurement of LNA(Low Noise Amplifier) based on GaN HEMT(Gallium Nitride High Electron Mobility Transistor) to reduce the total noise figure of radar receiver and for robustness of LNA. In radar receiver using LNA based on GaAs(Gallium Arsenide) technology, limiter is necessary at the very front of the radar receiver to protect LNA. As a result, total noise figure of radar receiver is deteriorated. In this research, measured noise figure of LNA based on GaN HEMT is below 2 dB. In the case of commercialized GaAs LNA, recommended maximum input power is about 30 dBm. On the other hand, GaN HEMT LNA which is designed and measured is burned-out when input power is 43 dBm and robustness is guaranteed at input power 45.4 dBm.

One Chip design of Electric Power Conversion Controller that use FPGA for SFCL(Superconducting Fault Current Limiter) (유도형 한류기를 위한 FPGA를 이용한 전력변환 제어기의 One Chip 설계)

  • 박근태;이양주;이창열;김동준
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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    • 2003.02a
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    • pp.189-192
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    • 2003
  • Inductivity Superconducting Fault Current Limiter is the Magnet that uses high temperature Superconductivity Coil. It is an important work that it controls Electric Power Converter of Inductivity SFCL. So, we wish to design the point part FPGA by One-Chip. Design of that can divide as following. One part that generate clock that offer to thyristor. One part that set 60Hz voltage to input Clock and do count. One part that change the value that require in CPU to the integer. And finally. there is part that send output (the fixed Clock) to the thyristor.

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Design of A Waveguide Limiter Having an Improved Attenuation and a Broadened Bandwidth by Using Multiple PIN-Diode Posts (다중 PIN-다이오드 포스트를 이용한, 향상된 감쇄량과 대역폭이 늘어난 도파관 리미터의 설계)

  • Kattak, Muhammad Kamran;Yoo, Seon-woong;Kahng, Sungtek;Yoo, Seongryong;Oh, DongChul;Roh, DonSuk;Yun, Songhyun
    • Journal of Satellite, Information and Communications
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    • v.10 no.3
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    • pp.26-31
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    • 2015
  • This paper deals with a size-reduced Ku-band waveguide limiter. Basically, it passes the signal from 16.125 GHz through 16.375 GHz, but when excessively high power is injected to the input port, it should change to a bandstop filter. Furthermore, it is required to change to bring attenuation by more than 20 dB and 50 dB over a narrow band and the entire passband, respectively. Therefore, in order to meet this requirement, a limiting device is implemented with multiple PIN-diode posts that enable the limiter to be the bandpass filter and stopband one at the off and on states of the PIN-diode switch, respectively. So, the design goes through the equivalent circuit modelling and the geometry is realized in the accurate electromagnetic analysis CAD tool. Finally, the result is discussed to shed light on whether it complies with the aforementioned requirement.

Current Limitation Characteristics of Josephson Junction Array (조셉슨 접합 어레이의 전류 차단특성)

  • Kang, C.S.;Kim, K.;Yu, K.K.;Lee, S.J.;Kwon, H.;Hwang, S.M.;Lee, Y.H.;Kim, J.M.;Lee, S.K.
    • Progress in Superconductivity
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    • v.10 no.2
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    • pp.144-148
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    • 2009
  • A current limiter was manufactured using a Josephson junction array to cut off an excessive current flowing into the SQUID sensor. The Fabricateed Josephson junction array was connected in series with a flux transformer that consists of a pick-up coil and an input coil, and the flux transformer was inductively coupled with a Double Relaxation Oscillation SQUID(DROS). The flux-voltage modulation curve was induced by applying an AC magnetic field whose magnitude was far smaller than that of the DC magnetic field. A change in the flux-voltage modulation curve of the SQUID was observed while the DC magnetic field was increased, to qualitatively examine the current limiting characteristic of the Josephson junction array. As a result, it was found that the SQUID flux-voltage modulation curve disappeared at the critical current of the Josephson junction array, which indicates that the Josephson junction array properly works as a current limiter.

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Development of Integrated Mixer Controller for Digital Public Address (디지털전관방송을 위한 통합믹서컨트롤러 개발)

  • Cho, Juphil;Kim, Kwan-Woong;Kim, Daeik
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.17 no.1
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    • pp.19-24
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    • 2017
  • Nowadays, based on the advancement of IT techniques, innovative products combining IT techniques to PA system are developing. In this paper, we presented the hybrid mixer controller for digital PA system. We develop the integrated mixer controller which includes the digital mixer composing an existing digital PA system and function of digital integrated controller. Developed integrated mixer controller consists of multichannel mixer function with 16 audio input channels, 8 output channels. And, it has an equalizer for processing digital audio signal, matrix and limiter. Also, the developed controller has some features such as internet connection for controlling of overall PA system and remote monitoring of mixer process condition.

광대역 고감도 DLVA 개발

  • 이두훈;김상진;김재연;조현룡;이정문;김상기
    • The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.4
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    • pp.39-52
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    • 2000
  • A design of 2 stage S-DLVA(successive detector log video amplifier) was studied to detect wide dynamic radar pulse ranging from -70 ㏈m to 0㏈m. A basic design idea was focused on the linear detection in logarithmic scale of wide dynamic range radar pulses from nosie-like weak power of -70 ㏈m to relatively high power 0 ㏈m. It is highly formidable, since it requires high speed detection less than 10 nsec over the operating frequency ranges from 6 to 18 ㎓. A limiter diode, a tunnel diode and an L17-C were used as a protecting device, a detector diode and a log video amplifier in companion as a single stage detector to give voltage output proportional to the input power of about 35 ㏈ dynamic range. A protype of 2-stage DLVA having one more single stage detector was fabricated with a 32 ㏈ low noise amplifier and a 3 ㏈ hybrid coupler to provide total 70 ㏈ dynamic range detection. The logging characteristics were measured to have log slope of 25m.V/㏈ against 70 ㏈ logging range from -55 ㏈m to +15 ㏈m, the log linearity of within +/- 1.5 ㏈, and tangential sensitivity was at -63 ㏈m. The pulse dynamics of rise time and recovery time were measured as 50 nsec and 1.2 $\mu$sec, respectively. The reason might be due to the parasitic capacitances of packaged limiter, tunnel diode, and L17-C.

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Fault Current Limitation Characteristics of the Bi-2212 Bulk Coil for Distribution-class Superconducting Fault Current Limiters (배전급 초전도 한류기 개발을 위한 Bi-2212 초전도 한류소자의 사고전류 제한 특성)

  • Sim, Jung-Wook;Lee, Hai-Gun;Yim, Sung-Woo;Kim, Hye-Rim;Hyun, Ok-Bae;Park, Kwon-Bae;Lee, Bang-Wook;Oh, Il-Sung;Kim, Ho-Min
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.2
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    • pp.277-281
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    • 2007
  • We investigated fault current limitation characteristics of the resistive superconducting fault current limiter (SFCL) which consisted of a Bi-2212 bulk coil and a shunt coil. The Bi-2212 bulk coil and the shunt coil were connected in parallel. The Bi-2212 bulk coil was placed inside the shunt coil to induce field-assisted quench. The fault test was conducted at an input voltage of $200V_{rms}$ and fault current of $12kA_{rms}\;and\;25kA_{rms}$. The fault conditions were asymmetric and symmetric, and the fault period was 5 cycles. The test results show that the SFCL successfully limited the fault current of $12kA_{rms}\;and\;25kA_{rms}$ to below $5.5{\sim}6.9kA_{peak}\;within\;0.64{\sim}2.17$ msec after the fault occurred. Limitation was faster under symmetric fault test condition due to the larger change rate of current. We concluded that the speed of fault current limitation was determined by the speed of current rise rather than the amplitude of a short circuit current. These results show that the Bi-2212 bulk coil is suitable for distribution-class SFCLS.

Error Rate Performance of DS-BPSK Signal transmitted through a Hard-Limiting Satellite Channel in the presence of Interference and Noise (간섭과 잡음이 존재하는 Hard-Limiting 위성채널상에서의 DS-BPSK신호의 오율특성)

  • 신동일;조성준
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.11 no.1
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    • pp.64-72
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    • 1986
  • The error rate equation fo DS-BPSK(Direct Sequence Binary Phase Shift Keying) signal transmitted through the nonlinear satellite transponder has been derived in the cochannel interference and downlink Gaussian noise environment. The input to the satellite transponder is the superposition of DS-BPSK signal with one interfere which is a cochannel wide-band PN signal. The error rate performance of DS-BPSK system has been evaluated and shown in figures in terms of carrier to interference power ratio(CIR), downlink signal to noise power ratio(downlink SNR) and process gain. In the analysis, it has been shown that the use of a hard limiter in DS-BPSK satellite system leads to the generation of narrow-band intermodulation products which is independent of the process gain. Also it is known that the error rate performance can be improved in the low levels (below 10dB) of CIR as the CIR increase. As the process gain varies from 10 to 100 the curve gives the about 10 dB gain in downlink SNR to maintain a fixed error rate.

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