• Smart Media Journal
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• v.11 no.10
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• pp.65-75
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• 2022

Deep learning is used as a creative tool that could overcome the limitations of existing analysis models and generate various types of results such as text, image, and music. In this paper, we propose a method necessary to preprocess audio data using the Niko's MIDI Pack sound source file as a data set and to generate music using Bi-LSTM. Based on the generated root note, the hidden layers are composed of multi-layers to create a new note suitable for the musical composition, and an attention mechanism is applied to the output gate of the decoder to apply the weight of the factors that affect the data input from the encoder. Setting variables such as loss function and optimization method are applied as parameters for improving the LSTM model. The proposed model is a multi-channel Bi-LSTM with attention that applies notes pitch generated from separating treble clef and bass clef, length of notes, rests, length of rests, and chords to improve the efficiency and prediction of MIDI deep learning process. The results of the learning generate a sound that matches the development of music scale distinct from noise, and we are aiming to contribute to generating a harmonistic stable music.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.904-911
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• 2003

A new method to reduce the size of microwave amplifiers spiral-shaped defected ground structure(Spiral-DGS) is proposed. A microstrip line having Spiral-DGS on the ground plane produces increased slow-wave factor and electrical length for the fixed physical length. In addition, it provides an excellent rejection characteristic for a finite frequency band like band rejection filters. The rejection band is used for rejecting harmonic components of amplifiers. The reduced microstrip line lengths in matching networks by Spiral-DGS are 39 % and 44 % of the original ones in input and output matching networks, respectively. It is shown that the measured S-parameters of the reduced amplifier agree well with those of the original amplifier. The measured second harmonic of the reduced amplifier is much less than that of the original amplifier by at least 10 dB. The same technique is applied to reject the third harmonic using the proper Spiral-DGS for the third harmonic frequency. The measured third harmonic is smaller than that of the original amplifier by 25 dB.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.69-78
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• 2017

Shannon of the 5G smartphone and Fourier of the signal processing meet in the sampling theorem (2 times the highest frequency 1). In this paper, the initial Shannon Theorem finds the Shannon capacity at the point-to-point, but the 5G shows on the Relay channel that the technology has evolved into Multi Point MIMO. Fourier transforms are signal processing with fixed parameters. We analyzed the performance by proposing a 2N-1 multivariate Fourier-Jacket transform in the multimedia age. In this study, the authors tackle this signal processing complexity issue by proposing a Jacket-based fast method for reducing the precoding/decoding complexity in terms of time computation. Jacket transforms have shown to find applications in signal processing and coding theory. Jacket transforms are defined to be $n{\times}n$ matrices $A=(a_{jk})$ over a field F with the property $AA^{\dot{+}}=nl_n$, where $A^{\dot{+}}$ is the transpose matrix of the element-wise inverse of A, that is, $A^{\dot{+}}=(a^{-1}_{kj})$, which generalise Hadamard transforms and centre weighted Hadamard transforms. In particular, exploiting the Jacket transform properties, the authors propose a new eigenvalue decomposition (EVD) method with application in precoding and decoding of distributive multi-input multi-output channels in relay-based DF cooperative wireless networks in which the transmission is based on using single-symbol decodable space-time block codes. The authors show that the proposed Jacket-based method of EVD has significant reduction in its computational time as compared to the conventional-based EVD method. Performance in terms of computational time reduction is evaluated quantitatively through mathematical analysis and numerical results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.368-376
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• 2006

This paper describes a Fcore_GenSim(Parameterized FFT Core Generation & Simulation Program), which can be used as an essential If(Intellectual Property) in various OFDM modem designs. The Fcore_Gensim is composed of two parts, a parameterized core generator(PFFT_CoreGen) that generates Verilog-HDL models of FFT cores, and a fixed-point FFT simulator(FXP_FFTSim) which can be used to estimate the SQNR performance of the generated cores. The parameters that can be specified for core generation are FFT length in the range of 64 ~2048-point and word-lengths of input/output/internal/twiddle data in the range of 8-b "24-b with 2-b step. Total 43,659 FFT cores can be generated by Fcore_Gensim. In addition, CBFP(Convergent Block Floating Point) scaling can be optionally specified. To achieve an optimized hardware and SQNR performance of the generated core, a hybrid structure of R2SDF and R2SDC stages and a hybrid algorithm of radix-2, radix-2/4, radix-2/4/8 are adopted according to FFT length and CBFP scaling.

• KIPS Transactions on Software and Data Engineering
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• v.5 no.11
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• pp.593-606
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• 2016

Computer simulation is widely used in a variety of computational science and engineering fields, including computational fluid dynamics, nano physics, computational chemistry, structural dynamics, and computer-aided optimal design, to simulate the behavior of a system. As the demand for the accuracy and complexity of the simulation grows, however, the cost of executing the simulation is rapidly increasing. It, therefore, is very important to lower the total execution time of the simulation especially when that simulation makes a huge number of repetitions with varying values of input parameters. In this paper we develop a simulation service system that provides the ability to predict the result of the requested simulation without actual execution for that simulation: by recording and then returning previously obtained or predicted results of that simulation. To achieve the goal of avoiding repetitive simulation, the system provides two main functionalities: (1) storing simulation-result records into database and (2) predicting from the database the result of a requested simulation using statistical machine learning techniques. In our experiments we evaluate the prediction performance of the system using real airfoil simulation result data. Our system on average showed a very low error rate at a minimum of 0.9% for a certain output variable. Using the system any user can receive the predicted outcome of her simulation promptly without actually running it, which would otherwise impose a heavy burden on computing and storage resources.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Korean Ceramic Society
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• v.41 no.11
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• pp.797-803
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• 2004

The heat generation tests of SiC and MO$_2$ samples by use of a microwave heating system were carried out and UO$_2$+5 wt% CeO$_2$ pellets were sintered in a microwave furnace in an oxidizing atmosphere, by taking into account the characteristics of the microwave heating obtained from the heat generation tests. The characteristics of pellets sintered in a microwave furnace were analysed and compared with those of the pellets sintered in a conventional electrical furnace. The temperature of MO$_2$ pellets with microwave heating increased quickly with input power and the variation of output power depended on the reaction characteristics of SiC and MO$_2$ with microwave. The sintered density of UO$_2$+5wt% CeO$_2$ pellets sintered in the microwave furnace was lower about 2% T.D. than that of the pellets sintered in an electrical furnace with sintering parameters. The microstructure of pellets sintered in microwave furnace has a broader pore distribution but has a larger grain size than that of the pellets sintered in the electrical furnace.

• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.58-62
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• 2010

This paper presents the effects of RF performance parameters on the Galileo receiver design via simulation after reviewing the requirements of the Galileo receiver structure. At first, we considered the general requirements, structure and characteristics of the Galileo system. Then we designed the Galileo receiver focused on performance requirement of 16 dB C/N which is equal to 15 % Error Vector Magnitude(EVM) by using Advanced Design System(ADS) simulation program. In order to verify the function of Automatic Gain Control(AGC)), we measured the IF output power level by changing the input power level at the front - end of the receiver. We analyzed the performance degradation due to phase noise variations of Local Oscillator(LO) in the Galileo receiver through EVM when the minimum sensitivity level of -127 dBm is applied at the receiver. We also analyzed the performance degradation according to variable Analog-to-Digital Converter(ADC) bits within the Dynamic range, -92 ~ -139 dBm, which has been defined by gain range (-2.5 ~ +42.5 dB) in the AGC operation. The results clearly show that the performance of the Galileo receiver can be improved by increasing ADC bits and reducing Phase Noise of LO.

• Journal of radiological science and technology
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• v.33 no.2
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• pp.97-107
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• 2010

The objectives of this study is to figure out the unknown image processing methods of commercial CR system. We have implemented the processing curve of each Look up table(LUT) in REGIUS 150 CR system by using virtual digital test pattern method. The characteristic of Dry Imager was measured also. First of all, we have generated the virtual digital test pattern file with binary file editor. This file was used as an input data of CR system (REGIUS 150 CR system, KONICA MINOLTA). The DICOM files which were automatically generated output files by the CR system, were used to figure out the processing curves of each LUT modes (THX, ST, STM, LUM, BONE, LIN). The gradation curves of Dry Imager were also measured to figure out the characteristics of hard copy image. According to the results of each parameters, we identified the characteristics of image processing parameter in CR system. The processing curves which were measured by this proposed method showed the characteristics of CR system. And we found the linearity of Dry Imager in the middle area of processing curves. With these results, we found that the relationships between the curves and each parameters. The G value is related to the slope and the S value is related to the shift in x-axis of processing curves. In conclusion, the image processing method of the each commercial CR systems are different, and they are concealed. This proposed method which uses virtual digital test pattern can measure the characteristics of parameters for the image processing patterns in the CR system. We expect that the proposed method is useful to analogize the image processing means not only for this CR system, but also for the other commercial CR systems.