• Title/Summary/Keyword: Input Signal Generation

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Electrical Characteristics Measurement of Eddy Current Testing Instrument for Steam Generator in NPP (원전 증기발생기 와전류검사 장치의 전기적 특성 측정)

  • Lee, Hee-Jong;Cho, Chan-Hee;Yoo, Hyun-Joo;Moon, Gyoon-Young;Lee, Tae-Hun
    • Journal of the Korean Society for Nondestructive Testing
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    • v.33 no.5
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    • pp.465-471
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    • 2013
  • A steam generator in nuclear power plant is a heatexchager which is used to convert water into steam from heat produced in a nuclear reactor core, and the steam produced in steam generator is delivered to the turbine to generate electricity. Because of damage to steam generator tubing may impair its ability to adequately perform required safety functions in terms of both structural integrity and leakage integrity, eddy current testing is periodically performed to evaluate the integrity of tubes in steam generator. This assessment is normally performed during a reactor refueling outage. Currently, the eddy current testing for steam generator of nuclear power plant in Korea is performed in accordance with KEPIC & ASME Code requirements, the eddy current testing system is consists of remote data acquisition unit and data analysis program to evaluate the acquired data. The KEPIC & ASME Code require that the electrical properties of remote data acquisition unit, such as total harmonic distortion, input & output impedance, amplifier linearity & stability, phase linearity, bandwidth & demodulation filter response, analog-to-digital conversion, and channel crosstalk shall be measured in accordance with the KEPIC & ASME Code requirements. In this paper, the measurement requirements of electrical properties for eddy current testing instrument described in KEPIC & ASME Code are presented, and the measurement results of newly developed eddy current testing instrument by KHNP(Korea Hydro & Nuclear Power Co., LTD) are presented.

A New Structural Carry-out Circuit in Full Adder (새로운 구조의 전가산기 캐리 출력 생성회로)

  • Kim, Young-Woon;Seo, Hae-Jun;Han, Se-Hwan;Cho, Tae-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.1-9
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    • 2009
  • A full adders is an important component in applications of digital signal processors and microprocessors. Thus it is imperative to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional static CMOS and pass transistor logic. The carry-out generation circuit of the proposed full adder is different from the conventional XOR-XNOR structure. The output Cout of module III is generated from input A, B and Cin directly without passing through module I as in conventional structure. Thus output Cout is faster by reducing operation step. The proposed module III uses the static CMOS logic style, which results full-swing operation and good driving capability. The proposed 1bit full adder has the advantages over the conventional static CMOS, CPL, TGA, TFA, HPSC, 14T, and TSAC logic. The delay time is improved by 4.3% comparing to the best value known. PDP(power delay product) is improved by 9.8% comparing to the best value. Simulation has been carried out using a $0.18{\mu}m$ CMOS design rule for simulation purposes. The physical design has been verified using HSPICE.

Enhanced Spatial Covariance Matrix Estimation for Asynchronous Inter-Cell Interference Mitigation in MIMO-OFDMA System (3GPP LTE MIMO-OFDMA 시스템의 인접 셀 간섭 완화를 위한 개선된 Spatial Covariance Matrix 추정 기법)

  • Moon, Jong-Gun;Jang, Jun-Hee;Han, Jung-Su;Kim, Sung-Soo;Kim, Yong-Serk;Choi, Hyung-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.5C
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    • pp.527-539
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    • 2009
  • In this paper, we propose an asynchonous ICI (Inter-Cell Interference) mitigation techniques for 3GPP LTE MIMO-OFDMA down-link receiver. An increasing in symbol timing misalignments may occur relative to sychronous network as the result of BS (Base Station) timing differences. Such symbol synchronization errors that exceed the guard interval or the cyclic prefix duration may result in MAI (Multiple Access Interference) for other carriers. In particular, at the cell boundary, this MAI becomes a critical factor, leading to degraded channel throughput and severe asynchronous ICI. Hence, many researchers have investigated the interference mitigation method in the presence of asynchronous ICI and it appears that the knowledge of the SCM (Spatial Covariance Matrix) of the asynchronous ICI plus background noise is an important issue. Generally, it is assumed that the SCM estimated by using training symbols. However, it is difficult to measure the interference statistics for a long time and training symbol is also not appropriate for MIMO-OFDMA system such as LTE. Therefore, a noise reduction method is required to improve the estimation accuracy. Although the conventional time-domain low-pass type weighting method can be effective for noise reduction, it causes significant estimation error due to the spectral leakage in practical OFDM system. Therefore, we propose a time-domain sinc type weighing method which can not only reduce the noise effectively minimizing estimation error caused by the spectral leakage but also implement frequency-domain moving average filter easily. By using computer simulation, we show that the proposed method can provide up to 3dB SIR gain compared with the conventional method.

A 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS ADC Based on High-Accuracy Integrated Capacitors (높은 정확도를 가진 집적 커페시터 기반의 10비트 250MS/s $1.8mm^2$ 85mW 0.13un CMOS A/D 변환기)

  • Sa, Doo-Hwan;Choi, Hee-Cheol;Kim, Young-Lok;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.11 s.353
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    • pp.58-68
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    • 2006
  • This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.