• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.685-697
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• 1997

A Viedo-on-Demand(VOD) service is a multimedia service that is realized by the rapid advance of computer and data communication techmologies. Basically, a VOD system is composed of a server and a number fo clients.The server stores and manages a large amount of digital moving picture data. Each slient sends an on-line requwet to the server and receives data for real-time displying. Many researches are performed on a VOD server using hard disks for the permanent video fata storage. However, a hard disk is less reliable and requires more storage cost than a massive storage device. Due to these resasons, a multi-level VOD system is proposed for using teh jukeboxes of optical disks as the permanent video storage,device. In this paper, we prpose the necessary software modules and protocols between the server and its clients for the implementation of the multi-level VOD server.

• Spatial Information Research
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• v.20 no.5
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• pp.67-76
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• 2012

Recently the mobile DBMS (Database Management System) is popular to store and manage large data in a mobile device. Especially, the research and development about mobile storage structure and querying method for navigation map data in a mobile device have been performed. The performance of the mobile DBMS in which random data accesses are most queries if the NAND flash memory is used as storage media of the DBMS is degraded. The reason is that the performance of flash memory is good in writing sequentially but bad in writing randomly as the features of the NAND flash memory. So, new storage structure and querying policies of the mobile DBMS are needed in the mobile DBMS in which a flash memory is used as storage media. In this paper, we have studied the policy of the database page management to enhance the performance of the frequent random update and applied this policy to the navigation-specialized mobile DBMS which supports incremental map update. And also we have evaluated the performance of this policy by experiments.

• Proceedings of the Korean Magnestics Society Conference
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• 2003.12a
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• pp.312-312
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• 2003

• Proceedings of the Korean Magnestics Society Conference
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• 2003.12a
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• pp.296-296
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• 2003

• Proceedings of the Korean Magnestics Society Conference
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• 2006.06a
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• pp.162-162
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• 2006

• Proceedings of the Korean Magnestics Society Conference
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• 2007.05a
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• pp.259.2-259.2
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• 2007

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.262-269
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• 2005

Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.5
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• pp.215-219
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• 2014

In holographic data storage (HDS), a high transmission rate is accomplished through the use of a charge coupled device array for reading two-dimensional (2D) pixel image data. Although HDS has many advantages in terms of storage capacity and data transmission rates, it also features problems, such as 2D intersymbol interference (ISI) by neighboring pixels and interpage interference (IPI) by multiple images stored in the same holographic volume. Modulation codes can be used to remove these problems. We introduce a 2D 8/9 error-correcting modulation code. The proposed modulation code exploits the trellis-coded modulation scheme, and the code rate is larger (about 0.889) than that of the conventional 6/8 balanced modulation code (an increase of approximately 13.9%). The performance of the bit error rate (BER) with the proposed scheme was improved compared with that of the 6/8 balanced modulation code and the simple 8/9 code without the trellis scheme.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.313-316
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• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.