• YAKHAK HOEJI
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• v.45 no.3
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• pp.282-286
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• 2001

To investigate the different mechanism between ATP and compound 48/80 (C$_{48}$80/)-induced histamine release, we observed effects of calcium antagonists in histamine release of rat peritoneal mast cells. Verapamil and diltiazem (voltage-dependent calcium channel blocker) and TMB-8 (a blocker of intracellular calcium release) significantly inhibited ATP-induced histamine release, but did not inhibit $C_{48}$80/-induced histamine release. Econazole (a blocker of receptor-operated calcium channel) dose-dependently inhibited both ATP and $C_{48}$80/-induced histamine release, but inhibitory effect of econazole in ATP-induced histamine release was more potent than that in $C_{48}$80/-induced histamine. EGTA dose-dependently inhibited ATP and $C_{48}$80/-induced histamine release, but $C_{48}$80/-induced histamine release was slightly inhibited by high concentrations (>2 mM) of EGTA. These results suggest that ATP-induced histamine release is related to broth intracellular calcium release and extracellular calcium influx via voltage-dependent calcium channel and receptor-operated calcium channel. $C_{48}$80/-induced histamine release is related to extracellular calcium influx, especially by receptor-operated calcium channel rather than voltage-dependent calcium channel.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.12
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• pp.903-913
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• 1988

Induced voltage causing disturbances on the communication lines of electric train is dealt with when the AT power supply system is employed. Induction interference is of three types, namely, normal state induced voltage, unusual induced voltage in case of power faults, and noise-induced voltage. Calculation of induced voltages occurring in the AT system is more complicated and extensive than in the BT system. In this paper we obtain an algorithm to calculate the induced voltages on the communication lines in the AT system and an algorithm for the induced current in case of the accident that the line falls to the ground. These algorithms are developed to a package of computer programs and their validity was checked on a simulated system. We supply the measures to protect the communication lines suitable for the AT system and we can also evaluate the protection capabilities. Because of the ability to evaluate the protection measures, this package is expected to be very useful when electric train system is constructed on communication lines near the railroad.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.406-414
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• 2014

Significant penetration of induction motor loads into residential neighborhood and commercial regions of local transmission systems at least partially determine a vulnerability to a fault induced delayed voltage recovery (FIDVR) event. Highly concentrated induction motor loads with constant torque could stall in response to low voltages associated with system faults. FIDVR is caused by wide spread stalling of small HVAC units (residential air conditioner) during transmission level faults. An under voltage load shedding scheme (UVLS) can be an effective component in a strategy to manage FIDVR risk and limit the any potential disturbance. Under Voltage Load Shedding take advantage of the plan to recovery the voltage of the system by shedding the load ways to alleviation FIDVR.

• Journal of information and communication convergence engineering
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• v.5 no.2
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• pp.150-154
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• 2007

Transponders of RFID system are classified as active or passive depending on the type of power supply they use. In passive transponders the data carrier has to obtain its power from the induced voltage. The induced voltage is converted into direct current using a low loss bridge rectifier and then smoothed. In practice, the induced voltage in the transponder coil is variable according to the coupling coefficient k and the load resistance ($R_L$). Therefore, the rectified voltage is unstable and the transponder of RFID is unstable sometimes. In this paper, a voltage-dependent shunt resistor ($R_s$) circuits are designed and inserted in parallel with the load resistance of RFID transponder in order to improve the stability of power.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2000.02a
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• pp.185-188
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• 2000

The voltage induced in the superconducting background magnet system is analyzed according to the calculation of self inductance and mutual inductance. The voltage induced by blip and compensation coils of the background magnet system is about 6.4V. In order to charge the main background magnet, the power supply must provide the minimum voltage of 1.1 kV. the compensation coils have an influence on the field distribution. The compensation coils result in the decreasing center field about 2.67%. It can remarkably decrease the ac losses and the voltage on the current leads of the background magnet.

• Journal of the Korean Magnetics Society
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• v.26 no.2
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• pp.62-66
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• 2016

We designed a model composed a ring type magnet, a yoke, and a sensing coil buried in a projectile for calculating the muzzle velocity based on the voltage induced from sensing coil by simulation. The muzzle velocity was calculated from the master curve obtained through the voltage induced from sensing coil by simulation. The induced voltage increased with increasing the diameter of sensing coil. The projectile's velocity was proportional to the induced voltage when the sensing coil was buried in projectile. The projectile will be surely exploded at the target region by inputting the information of muzzle velocity variation corrected the diameter effect of induced voltage of sensing coil.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.713-719
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• 2015

The change in induced voltage according to the relationship of ground connection between the aluminum sheath layer and a conductor pair in a general telecommunication cable is analyzed. When a measurement is practiced under the condition of separated sheath grounds with an averaged ground resistance of $42.6{\Omega}$, the induced voltage decreases 10 % to the induced voltage without sheath grounds. The induced voltage decreases approximately 50 % in the case of a one-sided common ground and decreases by more than 90 % in the case of a both-sided common ground. This experimental result is similar to the values calculated using the methods of the ITU Directives. In addition, according to a comparison analysis utilizing this ITU method, the measurement error range will be below 10 % in the state of ground resistance of central office less than $10{\Omega}$ and for the terminal side with $100{\Omega}$ less or more.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.7
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• pp.82-88
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• 1992

This paper presents one of the first comprehensive studies of how hot electron degradation impacts the input offset voltage of a CMOS differential amplifiers. This study utilizes the concept of a virtual source-coupled MOSFET pair in order to evaluate offset voltaged egradation directly from individual device measurement. Next, analytical models are developed to describe the offset voltage degradation. These models are used to examine how hot electron induced offset voltage is affected with the device parameters.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.428-431
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• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the IEEK Conference
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• summer
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• pp.209-212
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• 2004

In this paper, The stress induced leakage currents of thin silicon oxides is investigated in the nano scale structure implementation for Soc. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41\square\;and\;113.4\square,$ which have the channel width x length 10x1um, respectively. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.