• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.44-48
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• 2008

According to increment of stage, the speed of changeable stage Carry-increment adder can be close to $O(\sqrt{2n})$ because the word length which is computed in stage can be lengthened by 1 bit. But the number of stage bits is increased, fan-out of carry which is inputted in stage is increased. So tile speed can be slow. This paper presents a new carry-increment adder design method to fix the number of fan-outs regardless of the number of stages. By layout simulation of 37-bit adder, the area can be Increased up to 40%, but speed improvement up to 75% can be achieved, by the proposed method, compared with a conventional method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.47-55
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• 1997

In general, processing flow of the conventional floating-point multiplication consists of either multiplication, addition, normalization, and rounding stage of the conventional floating-point multiplier requries a high speed adder for increment, increasing the overall execution time and occuping a large amount of chip area. A floating-point multiplier performing addition and IEEE rounding in parallel is designed by using the carry select addder used in the addition stage and optimizing the operational flow based on the charcteristics of floating point multiplication operation. A hardware model for the floating point multiplier is proposed and its operational model is algebraically analyzed in this paper. The proposed floating point multiplier does not require and additional execution time nor any high spped adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this suggested approach.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.658-662
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• 2004

This paper proposes an orthogonal reception structure for OS/SS communication with time-shifted m-sequences, and compares the performances of the proposed and conventional receiver. This structure provides two important characteristics to reference user signal with not only increment of auto-correlation value but also cancel of the cross-correlation value out to zero between the reference user and other user signals. In addition, the structure can be easily implemented with the conventional receiver adding an additional integrator path in parallel and an adder that sums the conventional path output and the new path output signal. Hence, the proposed structure can be applied for channel impulse response measurement, and efficiently used for multi-user interference signal cancellation and channel capacity increment by flexible structural inter-working operation, connection or disconnection, of the new path to conventional receiver structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4A
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• pp.200-207
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• 2003

This paper proposes a CDMA receiver structure with time-shifted m-sequence orthogonal reception process, and analyzes the output SNR performance and the characteristics of the orthogonal receiver. This structure can be simply implemented with the converntional receiver adding an additional integrator path in parallel and an adder sums the conventional path and the new path output signals. The structure provides to reference user signal not only increment of signal component but also perfect orthogonal characteristic, canceling the accumulated cross-correlated value out to zero between the reference user and other user signals. Hence, the proposed structure can be applied for channel impulse response measurement, and used for multi-user interference signal cancellation and channel capacity increment by flexible structural inter-working operation of the added path, connection or disconnection, to conventional receiver structure.