• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.101-108
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• 2005

Adaptive constant false alarm rate(CFAR) algorithm is used for good detection probability as well as constant false alarm rate in clutter background. Especially, filtering technique adaptive to spatial variation is necessary for improving detection quality in non stationary clutter environment which has spatial correlation and large magnitude deviation. In this paper, we propose a two-dimensional block interpolation(TBI) adaptive CFAR algorithm that calculates the node estimate in the fred two dimensional region and subsequently determines the final estimate for each resolution cell by two-dimensional interpolation. The proposed method is efficient for filtering abnormal ejection by adopting distribution median in fixed region and also has advantage of reducing required memory space by using estimation method which gets final values after calculating the block node values. Through simulations, we show that the proposed method is superior to the traditional adaptive CFAR algorithms which are transversal or recursive in aspect of the detection performance and required memory space.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.3
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• pp.1-10
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• 2002

Because of the reduced number of displayable gray levels resulting from inverse gamma correction, images on a plasma display panel (PDP) exhibit undesirable false contours in dark areas. An error diffusion method has been applied to remedy this problem. However, it is computationally expensive and requires large memory resources. This paper proposes a computationally efficient dithering based technique to improve the gray level reproduction capability in dark areas. In the proposed method, multiple dithering masks ate utilized in turn to improve the gray level reproduction in dark areas. Also, in order to reduce undesirable regular patterns generated by the dithering method, positions of threshold values within a given dithering mask are changed. Compared to the error diffusion method, the proposed method requires much less computations and memory resources with a comparable gray level reproduction capability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.68-75
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• 2009

As the recent performance of microprocessor is improving quickly, the necessity of cache is growing because of the increase of the access time of main memory. Every block of direct-mapped cache maps to one cache line. Although the mapping rule is simple, if different blocks map to one cache line, the miss ratio will be higher than the set-associative cache due to conflicts. In this paper, for the improvement of the direct-mapped cache of OpenRISC, 4-way set-associative cache is proposed. Four blocks of the main memory of the proposed cache map to one cache line so that the miss ratio is less than the direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The OpenRISC core including the 4-way set-associative cache was verified with FPGA emulation. As the result of performance measurement using test program, the performance of the OpenRISC core including the 4-way set-associative cache is higher than the previous one by 50% and the decrease of miss ratio is more than 15%.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.3-10
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• 2017

Counting Bloom filters (CBFs) have been popularly used in many network algorithms and applications for the membership queries of dynamic sets, since CBFs can provide delete operations, which are not provided in a standard 1-bit vector Bloom filter. However, because of the counting functions, a CBF can have overflows and accordingly false negatives. CBFs composed of 4-bit counters are generally used, but the 4-bit CBF wastes memory spaces by allocating 4 bits for every counter. In this paper, we propose a simple alternative of a 4-bit CBF named ternary Bloom filter (TBF). In the proposed TBF structure, if two or more elements are mapped to a counter in programming, the counters are not used for insertion or deletion operations any more. When the TBF consumes the same amount of memory space as a 4-bit CBF, it is shown through simulation that the TBF provides a better false positive rate than the CBF as well as the TBF does not generate false negatives.

• Journal of Korea Spatial Information System Society
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• v.11 no.2
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• pp.89-98
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• 2009

As data stream is entered into system continuously and the memory space is limited, the data exceeding the memory size cannot be processed. In order to solve the problem, load shedding methods which drop a part of data to prevent exceeding the storage space have been researched. Generally, a traditional load shedding method uses random sampling with optimized rate according to data deviation. The method samples data not to distinguish those used in spatial query because the method uses only a random sampling with optimized rate according to data deviation. Therefore, the accuracy of query was reduced in u-GIS environment including spatial query. In this paper, we researched a new load shedding method improving accuracy of the query in u-GIS environment which runs spatial query and aspatial query simultaneously. The method uses a new sampling method that samples data having low probability used in query. Therefore proposed method improves spatial query accuracy and query processing speed as applying spatial filtering operation to sampling operator.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.11
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• pp.1429-1436
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• 1999

데이타들에 대한 선인출 효과를 얻기 위하여 캐쉬 메모리의 캐쉬 블록은 다중 워드로 구성된다. 그러나 선인출된 데이타들이 사용되지 않을 경우 캐쉬 메모리가 낭비되고 따라서 캐쉬 실패율이 증가한다. 데이타 배열 병합 방법은 캐쉬 실패 원인의 하나인 캐쉬 충돌 실패를 감소시키기 위하여 사용되고 있다. 그러나 기존의 배열 병합 방법은 유용하지 못한 데이타들을 캐쉬 블록에 선인출하는 현상을 보인다. 본 논문에서는 이러한 현상을 개선한 스트라이드 배열 병합을 제안한다. 모의시험에서 캐쉬 블록이 다중 워드로 구성된 경우 스트라이드 배열 병합은 캐쉬 충돌 실패를 감소시킬 뿐 만 아니라 유용한 데이타 선인출을 증가 시키므로 캐쉬 성능을 향상시킴을 보여준다. 또한 이렇게 향상된 캐쉬 성능은 프로세서 증가에 따른 확장성 있는 프로그램 성능을 나타낸다.Abstract The cache memory is composed of cache lines with multiple words to achieve the effect of data prefetching. However, if the prefetched data are not used, the spaces of the cache memory are wasted and thus the cache miss rate increases. The data merging-arrays method is used for the sake of the reduction of the cache conflict misses. However, the existing merging-arrays method results in the useless data prefetching. In this paper, a stride merging-arrays method is suggested for improving this phenomenon. Simulation results show that when a cache line is composed of multiple words, the stride merging-arrays method increases the cache performance due to not only the reduction of cache conflict misses but also the useful data prefetching. This enhanced cache performance also represents the more scalable performance of parallel applications according to increasing the number of processors.

• Journal of KIISE
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• v.41 no.11
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• pp.878-884
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• 2014

File I/O buffer cache plays an important role in narrowing the wide speed gap between the main memory and the secondary storage. However, data loss or inconsistencies may occur if the system crashes before the data that has been updated in the buffer cache is flushed to storage. Thus, most operating systems adopt a daemon that periodically flushes dirty data to the secondary storage. In this study, we show that periodic flushes account for 30-70% of the total write traffic to storage and remove this inefficiency by implementing a small, non-volatile buffer cache. Specifically, we present space-efficient management techniques, such as delta-write and fragment-grouping, and show that the storage write traffic and throughput can be improved by a margin of 44.2% and 23.6%, respectively, with only a small NVRAM.

• Journal of KIISE
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• v.44 no.8
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• pp.767-773
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• 2017

In a distributed system environment, such as a cloud database, the tail latency needs to be kept short to ensure uniform quality of service. In this paper, through experiments on a Cassandra database, we show that long tail latency is caused by a lack of memory space because the database cannot receive any request until free space is reclaimed by writing the buffered data to the storage device. We observed that, since the performance of the storage device determines the amount of time required for writing the buffered data, the performance degradation of Solid State Drive (SSD) due to garbage collection results in a longer tail latency. We propose a garbage collection synchronization technique, called SyncGC, that simultaneously performs garbage collection in the java virtual machine and in the garbage collection in SSD concurrently, thus hiding garbage collection overheads in the SSD. Our evaluations on real SSDs show that SyncGC reduces the tail latency of $99.9^{th}$ and, $99.9^{th}-percentile$ by 31% and 36%, respectively.

• The Korean Journal of Physiology and Pharmacology
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• v.15 no.6
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• pp.333-338
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• 2011

Black ginseng (BG) has been widely used as herbal treatment for improving physiological function. In order to investigate the neuroprotective action of this herbal medicine, we examined the influence of BG on the learning and memory of rats using the Morris water maze, and we studied the effects of BG on the central cholinergic system and neural nitric oxide synthesis in the hippocampus of rats with neuronal and cognitive impairment. After middle cerebral artery occlusion was applied for 2h, the rats were administered BG (100 or 400 $mgkg^{-1}$, p.o.) daily for 2 weeks, followed by training and performance of the Morris water maze test. The rats with ischemic insults showed impaired learning and memory on the tasks. Treatment with BG produced improvement in the escape latency to find the platform. Further, the BG groups showed a reduced loss of cholinergic immunoreactivity and nicotinamide adenine dinucleotide phosphate-diaphorase (NADPH-d)-positive neurons in the hippocampus compared to that of the ISC group. These results demonstrated that BG has a protective effect against ischemia-induced neuronal and cognitive impairment. Our results suggest that BG might be useful for the treatment of vascular dementia.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11B
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• pp.1329-1338
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• 2011

This paper proposes an algorithm and hardware architecture for a broadcast communication which has the worst bottleneck among multiprocessor using distributed memory architectures. In conventional systems, collective communication is converted into point-to-point communications by MPI library cell without considering the state of communication port of each processing node which represents the processing node is in busy state or free state. If conflicting point-to-point communication occurs during broadcast communication, the transmitting speed for broadcast communication is decreased. Thus, this paper proposed an algorithm which determines the order of point-to-point communications for broadcast communication according to the state of each processing node. According to the state of each processing node, the proposed algorithm decreases total broadcast communication time by transmitting message preferentially to the processing node with communication port in free state. The proposed MPI unit for broadcast communication is evaluated by modeling it with systemC. In addition, it achieved a highly improved performance for broadcast communication up to 78% with 16 nodes. This result shows the proposed algorithm is useful to improving total performance of MPSoC.