• Journal of the Korea Society of Computer and Information
• /
• v.18 no.10
• /
• pp.97-107
• /
• 2013

The latest programming paradigm has been mostly geared toward object-oriented programming and visual programming based on the object-oriented programming. However, object-oriented programming has a more difficult and complicated concept compared with that of existing structural programming technique; thus it has been very difficult to educate students in the IT-related department. This study designed and implemented a Java robot training kit in which the Java virtual machine is built so that it may enhance the desire and motivation of students for learning the object-oriented programming using the training kit which is possible to attach various input and output devices and to control a robot. The developed Java robot training kit is able to communicate with a computer through the USB interface, and it also enables learners to manufacture a robot for education and to practice applied programming because there is a general purpose input and output port inside the kit, through which diverse input and output devices, DC motor, and servo motor can be operated. Accordingly, facing the IT fusion era, the wall between the academic circles and the major becomes lower and the need for introducing education about creative engineering object-oriented programming language is emerging. At this point, the Java robot training kit developed in this study is expected to make a great commitment in this regard.

• Journal of the Korea Society of Computer and Information
• /
• v.16 no.11
• /
• pp.1-8
• /
• 2011

The requirement of a system-on-a-chip (SoC) design is increasing, which combines various and complex functional units on a single device. However, short time to market prohibits to release the device. To satisfy this shorter time-to-market, verification of both hardware and software at the same time is important. A virtual platform-based design method supports faster verification of these combined software and hardware by reusing pre-defined intellectual properties (IP). In this paper, we introduce the virtual platform-based design and redesign the existing ARM processor based S3C2440A system using the virtual platform-based method. In addtion, we implement and evaluate the performance of a JPEG decoder on the S3C2440A virtual platform. Furthermore, we introduce an optimized technique of the JPEG decoder using the ARM based inline assembly language, and then verify the performance improvement on the virtual platform. Such virtual platform-based design allows to verify both software and hardware at the same time and can meet the requirement of the shorter time-to-market.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.7 s.349
• /
• pp.143-149
• /
• 2006

Turbo code, a kind of error correction coding technique, has been used in the field of digital mobile communication system. As the number of iterations increases, it can achieves remarkable BER performance over AWGN channel environment. However, if the number of iterations is increased in the several channel environments, any further iteration results in very little improvement, and requires much delay and computation in proportion to the number of iterations. To solve this problems, it is necessary to device an efficient criterion to stop the iteration process and prevent unnecessary delay and computation. In this paper, it proposes an efficient and simple criterion for stopping the iteration process in turbo decoding. By using sign changed ratio of extrinsic information values in turbo decoder, the proposed algorithm can largely reduce the average number of iterations without BER performance degradation. As a result of simulations, the average number of iterations is reduced by about $12.48%{\sim}22.22%$ compared to CE algorithm and about $20.43%{\sim}54.02%$ compared to SDR algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.7 s.361
• /
• pp.71-80
• /
• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• The Journal of Society for e-Business Studies
• /
• v.19 no.4
• /
• pp.135-150
• /
• 2014

As the collection and use of personal information increases, the accidents that abuse and leak personal information are continuously increasing. The nation has established new laws and strengthened related laws for the prevention of the mass leakage of personal information and the secondary damage due to the leaked personal information. The nation also established the guidelines that need to be implemented by the institutions handling personal information for the safety of the personal information. For the efficient implementation of guidelines under the limited time and resources, it is necessary to establish the priorities between guidelines. This paper compares the relative importance of the guidelines by AHP (Analytic Hierarchy Process) technique. We performed the analysis on two expert groups, the group of consultants working in information security consulting company and the group of information security staffs handling personal information directly in the company. We compared the differences between groups and recommended the relative importances of the guidelines.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.11A
• /
• pp.1827-1840
• /
• 2001

In digital data transmission/storage systems, the compensation for channel distortion is conducted normally using a training sequence that is known a priori to both the sender and receiver. The use of the training sequences results in inefficient utilization of channel bandwidth. Sometimes, it is also impossible to send training sequences such as in the burst-mode communication. As such, a great deal of attention has been given to the approach requiring no training sequences, which has been called the blind equalization technique. On the other hand, to utilize the limited bandwidth effectively, the concept of partial response (PR) signaling has widely been adopted in both the high-speed transmission and high-density recording/playback systems such as digital microwave, digital subscriber loops, hard disk drives, digital VCRs and digital versatile recordable disks and so on. This paper is concerned with blind adaptive equalization of partial response channels whose transfer function zeros are located on the unit circle, thereby causing some problems in performance. Specifically we study how the problems of blind channel equalization associated with the PR channels can be improved. In doing so, we first discuss the existing methods and then propose new structures for blind PR channel equalization. Our structures have been extensively tested by computer simulation and found out to be encouraging in performance. The results seem very promising as well in terms of the implementation complexity compared to the previous approach reported in literature.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.1
• /
• pp.73-80
• /
• 2004

In this paper, the implementation and embedding method of the existing air-filled waveguide-filters at millimeter-wave on general PCB substrate is introduced by systematically inserting the vias inside waveguide and mathematically manipulating the simple equations obtained ken the classical circular-post waveguide filter design. All the metal structures placed vertically such as side wall fur perfect ground plane and circular-post for signal control in the air-filled WR-22 waveguide are replaced with several types of via for constructing the bandpass-filter. Side wall and poles inside waveguide are realized by placing a series array of via and tuning the via diameter. The lengths of x, y, z axis are reduced in proportion to root square of employed substrate dielectric constant and especially the length of z axis can be more reduced due to the characteristics of the wave propagation. Because the mass production on PCB is possible without fabricating a large-scaled metal waveguide of WR-22 as input/output ports at millimeter-wave regime, the manufacturing cost is reduced considerably. Finally, when using multilayer process like LTCC for small-sized module, it is one of advantages to use only one layer f3r the filter fabrication. To evaluate the validity of this novel technique, order-3 Chebyshev BPF(Bandpass-Filter) centered at 40 GHz-band with a 2.5 ％ FBW (Fractional Bandwidth) were used. The employed substrate has relative dielectric constant of 2.2 and thickness of 10 mil of Rogers RT/Duroid 5880. Accroding to design and measurement results, a good performance of insertion loss of 2 ㏈ and return loss of -30 ㏈ is achieved at full input/output ports.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.1
• /
• pp.1-10
• /
• 2001

In this paper, a multistage parallel interference canceller (MPIC) and a partial multistage parallel interference canceller (PMPIC) are employed as a technique for improving the performance of the asynchronous DS-CDMA systems. The degree of the effect of the timing errors and phase errors on the interference cancellation capability of two types of cancellers is theoretically analyzed and the computer simulation is performed to confirm the analytical results. From the results, the large performance improvement is obtained by employing MPIC and PMPIC with perfect synchronization over the conventional matched filter, and the performance improvement obtained by MPIC and PMPIC is very close to each other as the number of the stage of MPIC and PMPIC increases. When the timing errors and phase errors are considered (in the case of imperfect synchronization), the performance improvement reduces as the performance degradation at the first stage (no cancellation) has a bad effect on the decision statistics at each stage. However MPIC and PMPIC have the strong interference cancellation capability in spite of imperfect synchronization as the number of the stage increases. An interference canceller, which has the strong interference cancellation capability as well as lower complexity for the implementation, is needed for practical systems with timing errors and phase errors because the perfect synchronization is impossible. Therefore, the excellent tradeoff between complexity and performance offered by PMPIC makes it an attractive approach for practical systems.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.4
• /
• pp.906-911
• /
• 2004

In this paper, a VCDRO(Voltage Control Dielectric Resonator Oscillator) applied to FMCW(Frequency Modulated Continuous Wave)Radar as stable source is implemented and constructed with a MESFET(Metal-semiconductor Field-Effect Transistor) for low noise, a dielectric resonate. of high frequency selectivity, and high Q varator diode to obtain a good phase noise performance and stable sweep characteristics. The designed circuits is simulated thrash harmonic balance simulation technique to provide the optimum performance. The measured result of a fabricated VCDRO shows that output is 2.22㏈m at 12.05GHz, harmonic suppression -30㏈c, phase noise -130㏈c at 100KHz offset, and sweep range of varator diode $\pm$18.7MHz, respectively. This oscillator will be available to FMCW Radar.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.7
• /
• pp.1821-1841
• /
• 1997

This paper presents an automated protocol conformance test sequence generation based on formal methods for LOTOS specification by using and applying many existing related algorithms and technique, such as the testing framework, Rural Chinese Postman tour concepts. We use the state-transition graphs obtained from LOTOS specifications by means of the CAESAR tool. This tool compiles a specification written in LOTOS into an extended Petri net, from which a transition graph of a event finite-state machine(EvFSM) including data is generated. A new characterizing sequence(CS), called Unique Event sequence(UE sequence) is defined. An UE sequence for a state is a sequence of accepted gate events that is unique for this state. Some experiences about UE sequence, partial UE sequence and signature are also explained. These sequences are combined with the concept of the Rural Chinese Postman Tour to obtain an optimal test sequence which is a minimum cost tour of the reference transition graph of the EvFSM. This paper also presents a fault coverage estimation experience of an automated method for optimized test sequences generation and the translation of the test sequence obtained by using our tool to TTCN notation are also given. A prototype of the proposed framework has been built with special attention to real application in order to generated the executable test cases in an automatic way. This formal method on conformance testing can be applied to the protocols related to IN, PCS and ATM for the purpose of verifying the correctness of implementation with respect to the given specification.