• Title/Summary/Keyword: Implementation technique

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A Study on Design and Implementation of Driver's Blind Spot Assist System Using CNN Technique (CNN 기법을 활용한 운전자 시선 사각지대 보조 시스템 설계 및 구현 연구)

  • Lim, Seung-Cheol;Go, Jae-Seung
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.2
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    • pp.149-155
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    • 2020
  • The Korea Highway Traffic Authority provides statistics that analyze the causes of traffic accidents that occurred since 2015 using the Traffic Accident Analysis System (TAAS). it was reported Through TAAS that the driver's forward carelessness was the main cause of traffic accidents in 2018. As statistics on the cause of traffic accidents, 51.2 percent used mobile phones and watched DMB while driving, 14 percent did not secure safe distance, and 3.6 percent violated their duty to protect pedestrians, representing a total of 68.8 percent. In this paper, we propose a system that has improved the advanced driver assistance system ADAS (Advanced Driver Assistance Systems) by utilizing CNN (Convolutional Neural Network) among the algorithms of Deep Learning. The proposed system learns a model that classifies the movement of the driver's face and eyes using Conv2D techniques which are mainly used for Image processing, while recognizing and detecting objects around the vehicle with cameras attached to the front of the vehicle to recognize the driving environment. Then, using the learned visual steering model and driving environment data, the hazard is classified and detected in three stages, depending on the driver's view and driving environment to assist the driver with the forward and blind spots.

Implementation of High-Throughput SHA-1 Hash Algorithm using Multiple Unfolding Technique (다중 언폴딩 기법을 이용한 SHA-1 해쉬 알고리즘 고속 구현)

  • Lee, Eun-Hee;Lee, Je-Hoon;Jang, Young-Jo;Cho, Kyoung-Rok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.4
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    • pp.41-49
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    • 2010
  • This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.

Implementation of a QoS routing path control based on KREONET OpenFlow Network Test-bed (KREONET OpenFlow 네트워크 테스트베드 기반의 QoS 라우팅 경로 제어 구현)

  • Kim, Seung-Ju;Min, Seok-Hong;Kim, Byung-Chul;Lee, Jae-Yong;Hong, Won-Taek
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.9
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    • pp.35-46
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    • 2011
  • Future Internet should support more efficient mobility management, flexible traffic engineering and various emerging new services. So, lots of traffic engineering techniques have been suggested and developed, but it's impossible to apply them on the current running commercial Internet. To overcome this problem, OpenFlow protocol was proposed as a technique to control network equipments using network controller with various networking applications. It is a software defined network, so researchers can verify their own traffic engineering techniques by applying them on the controller. In addition, for high-speed packet processing in the OpenFlow network, programmable NetFPGA card with four 1G-interfaces and commercial Procurve OpenFlow switches can be used. In this paper, we implement an OpenFlow test-bed using hardware-accelerated NetFPGA cards and Procurve switches on the KREONET, and implement CSPF (Constraint-based Shortest Path First) algorithm, which is one of popular QoS routing algorithms, and apply it on the large-scale testbed to verify performance and efficiency of multimedia traffic engineering scheme in Future Internet.

Implementation of the BLDC Motor Drive System using PFC converter and DTC (PFC 컨버터와 DTC를 이용한 BLDC 모터의 구동 시스템 구현)

  • Yang, Oh
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.44 no.5
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    • pp.62-70
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    • 2007
  • In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

Development of an OLAP Database System for Calculating National Information Security Index Numbers (국가 정보보호 지수 산출을 위한 OLAP 데이터베이스 시스템의 구축)

  • Choi, Jung-Woo;Choi, In-Soo
    • Journal of the Korea Society of Computer and Information
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    • v.16 no.12
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    • pp.285-296
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    • 2011
  • UN, OECD, ITU and other international organizations regularly announce ISI (Information Society Index) to utilize in establishing and evaluating information policies. ISI is utilized as important data for countries to evaluate their information policy performance and select future projects. As the advancement of information systems, the importance of information security has been emerged. Accordingly, NISI (National Information Security Index) has been required. NISI number is the most clearly figure to express the characteristics of a particular group's information security. It can be utilized in determining information security policies. Currently, questionnaire method has been used to calculate NISI number. But there is an absolute lack of statistical data, and the reliability of surveyed statistical data is problematic. The objective of this paper is to show how to collect precise micro data of each company's information security index numbers, and to develop an OLAP database system which calculating NISI numbers by using those micro data. In this process of the survey, we presented the technique to collect the data more systematically, and to analyze the data without using questionnaire method. OLAP architecture performs only well on the facts that are summarizable along each dimension, where all hierarchy schemas are distributive. Therefore we transformed the non-distributive hierarchy schema into the distributive hierarchy schema to implement OLAP database system. It is thought that this approach will be useful one from an implementation and schema design point of view.

Model Study of the Fate of Hydrocarbons in the Soil-Plant Environment (녹지 토양내 탄화수소화합물의 분포변화에 관한 모델링 연구)

  • Yoon-Young Chang;Kyung-Yub Hwang
    • Journal of Korea Soil Environment Society
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    • v.1 no.2
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    • pp.91-101
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    • 1996
  • In recent years, phytoremediation, the use of plants to detoxify hydrocarbons, has been a promising new area of research, particularly in situ cleanup of large volumes of slightly contaminated soils. There is increasing need for a mathematical model that can be used as a predictive tool prior to actual field implementation of such a relatively new technique. Although a number of models exist for solute-plant interaction in the vegetated zone of soil, most of them have focused on ionic nutrients and some metals. In this study, we developed a mathematical model for simulation of bioremediation of hydrocarbons in soil, associated with plant root systems. The proposed model includes root interactions with soil-water and hydrocarbons in time and space, as well as advective and dispersive transport in unsaturated soil. The developed model considers gas phase diffusion and liquid-gas mass exchanges. For simulation of temporal and spatial changes in root behavior on soil-water and with hydrocarbons, time-specific distribution of root quantity through soil was incorporated into the simulation model. Hydrocarbon absorption and subsequent uptake into roots with water were simulated with empirical equations. In addition, microbial activity in the rhizosphere, a zone of unique interaction between roots and soil microorganisms, was modeled using a biofilm theory. This mathematical model for understanding and predicting fate and transport of compound in plant-aided remediation will assist effective application of plant-aided remediation to field contamination.

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A Development of the Evaluation Index for UTIS Traffic Information Service (UTIS 교통정보 제공서비스 성과평가 인덱스 개발)

  • Kim, Eun-Jeong;Bae, Kwang-Soo;Ahn, Gye-Hyeong;Lee, Chul-Ki
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.9 no.6
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    • pp.13-21
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    • 2010
  • Road Traffic Authority and National Police Agency is currently managing the "development of an integrated metropolitan traffic information infrastructure" that installs of facilities for a traffic information infrastructures, such as Local Traffic Information Center, UTIS(Urban Traffic Information System), CCTV, VMS and etc. CTIC was established in 2005 to act as an traffic information hub and to provide integrated UTIS traffic information without regional barriers. This study was carried out to seek for solution to improve quality of UTIS traffic information service for the Central Traffic Information Center(CTIC). In this study, the Evaluation index for UTIS traffic information service was developed and the implementation plan was established by using requirement analysis method, case study and AHP(Analytic Hierarchy Process) technique. The Evaluation index consist of 5 fields and 20 index, it make possible evaluation of direct/indirect effect for UTIS traffic information service. In conclusion, It is expected that quality of UTIS traffic information service will be improved by using developed evaluation index and also can be applied for performance evaluation of other traffic information systems.

The Implementation of Digital Neural Network with identical Learning and Testing Phase (학습과 시험과정 일체형 신경회로망의 하드웨어 구현)

  • 박인정;이천우
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.4
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    • pp.78-86
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    • 1999
  • In this paper, a distributed arithmetic digital neural network with learning and testing phase implemented in a body has been studied. The proposed technique is based on the two facts; one is that the weighting coefficients adjusted will be stored in registers without shift, because input values or input patterns are not changed while learning and the other is that the input patterns stored in registers are not changed while testing. The proposed digital neural network is simulated by hardware description language such as VHDL and verified the performance that the neural network was applied to the recognition of seven-segment. To verify proposed neural networks, we compared the learning process of modified perceptron learning algorithm simulated by software with VHDL for 7-segment number recognizer. The results are as follows: There was a little difference in learning time and iteration numbers according to the input pattern, but generally the iteration numbers are 1000 to 10000 and the learning time is 4 to 200$\mu\textrm{s}$. So we knew that the operation of the neural network is learned in the same way with the learning of software simulation, and the proposed neural networks are properly operated. And also the implemented neural network can be built with less amounts of components compared with board system neural network.

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CoAP-based Time Synchronization Algorithm in Sensor Network (센서 네트워크에서의 CoAP 기반 시각 동기화 기법)

  • Kim, Nac-Woo;Son, Seung-Chul;Park, Il-Kyun;Yu, Hong-Yeon;Lee, Byung-Tak
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.3
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    • pp.39-47
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    • 2015
  • In this paper, we propose a new time synchronization algorithm using CoAP(constrained-application protocol) in sensor network environment, which handles a technique that synchronizes an explicit timestamp between sensor nodes not including an additional module for time-setting and sensor node gateway linked to internet time server. CoAP is a standard protocol for sensor data communication among sensor nodes and sensor node gateway to be built much less memory and power supply in constrained network surroundings including serious network jitter, packet losses, etc. We have supplied an exact time synchronization implementation among small and cheap IP-based sensor nodes or non-IP based sensor nodes and sensor node gateway in sensor network using CoAP message header's option extension. On behalf of conventional network time synchronization method, as our approach uses an exclusive protocol 'CoAP' in sensor network, it is not to become an additional burden for synchronization service to sensor nodes or sensor node gateway. This method has an average error about 2ms comparing to NTP service and offers a low-cost and robust network time synchronization algorithm.

The Performance Analysis of Distributed Reorder Buffer in Superscalar Processor using Analytical Model (해석적 모델을 이용한 분산된 리오더 버퍼 슈퍼스칼라 프로세서의 성능분석)

  • Yoon, Wan-Oh;Shin, Kwang-Sik;Kim, Kyeong-Seob;Lee, Yun-Sub;Choi, Sang-Bang
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.12
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    • pp.73-82
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    • 2008
  • There are several approaches for reducing the ROB(Reorder Buffer) complexity in processors. The one technique that makes the simplest ROB ports relies on a distributed implementation that spreads the centralized ROB structure across the functional units(FUs). Each distributed buffers are decided on the size of them by workload of the functional units. The performance of the processor depends on the size of distributed ROB. However, most of previous works have depended on the simulation results to decide the optimsize of distributed ROB. In this Paper, we use an analytical model based on the M/M/1 Queuing theory to determine the optimum size of each distributed ROB. Our schemes are evaluated by using the simulation performed by the CPU2000 benchmarks. We are able to choose the optimum size of distributed ROB showing the 99.2% performance compared with existing superscalar processors. We can save 82% hardware resources in ports and reduce more than 30% of delay when ROB and distributed ROB proposed in this paper are designed by HDL.