• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.90-93
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• 2002

In this work, an efficient lifting implementation of invertible deinterlacing is proposed. The invertible deinterlacing is a technique developed for intra-frame-based video coding as a preprocessing. Unlike the conventional deinterlacing, it preserves the sampling density and has the invertibility. For a special selection of filters, it is shown that the deinterlacing can be implemented efficiently by an in-place computation. It is also shown that the deinterlacing can be combined with the lifting discrete wavelet transform (BWT) employed in JPEG2000. A bit modification of the original lifting DWT is shown to provide the simultaneous implementation of deinterlacing. This fact makes the proposed technique attractive for the application to Motion-JPEG2000. The inverse transform and the reversible lifting implementation are also discussed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.219-227
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• 2012

This paper describes the design and implementation of an efficient image security system for CCTV using the analysis technique of color informations. In conventional approaches, the compression and encryption techniques are mainly used for reducing the data size of the original images while the analysis technique of color information is first proposed, which eliminates the overlapping part of the original image data in our approach. In addition, security-enhanced CCTV image security system is presented using SSL/VPN tunneling technique. When we use the method proposed in this paper, an efficient image processing is enable for a mount of information, and also security problem is enhanced. Through the implementation results, the proposed method showed that the original image information are dramatically reduced.

• The Journal of Asian Finance, Economics and Business
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• v.7 no.10
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• pp.1035-1046
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• 2020

This study aims to find empirical evidence of causal relationship between strategy type, market orientation, strategic management accounting (SMA) strategic costing technique, and financial sector performance of private universities in Indonesia. The research object in this study are private universities in Yogyakarta, Indonesia. Yogyakarta is chosen because universities there are one of the barometers of higher education in Indonesia, and the city has quite a number of universities. The respondents in this study are the leader (manager) of private universities in Yogyakarta, Indonesia. The data analysis is done using SEM-PLS with WarpPLS 3.0 software. The results of this study show that market orientation has significant influence on the development and implementation of SMA strategic costing technique, while strategy type does not have significant influence on the development and implementation of SMA strategic costing technique. This study also finds that the implementation of SMA strategic costing technique significantly influences the financial sector performance of private universities in Yogyakarta, Indonesia. This study provides theoretical implication regarding SMA development in universities that consider that contingency factors (market orientation) can encourage increased organizational performance. It indicates support for contingency theory that states there are no general principles that apply to all situations.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.737-740
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• 1998

Under the worldwide booming internet environment, there has been increasing demand for various multimedia services. Especially the demand for effective video services has been rapidly increased. In this paper, we describe the implementation of video service system for internet use based on H/263 video compression technique and UDP socket on the TCP/IP environment. In addition, by using the plug-in-play technique, the implemented system improved user interface for correct retrieval and easy usage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1053-1056
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• 2005

This paper proposes a design technique of DDS (Direct Digital Synthesizer) to reduce the ROM size, and also describes the procedure of the implementation of the technique. Unlike other techniques suggested so far, the proposed technique is able to reduce the ROM size to a great extent with minimal hardware overheads. The frequencies of the signal synthesized by the implemented DDS accurately changed with the applied frequency control words.

• ETRI Journal
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• v.43 no.4
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• pp.746-757
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• 2021

Side-channel attacks pose an inevitable challenge to the implementation of cryptographic algorithms, and it is important to mitigate them. This work identifies a novel data encoding technique based on 1-of-4 codes to resist differential power analysis attacks, which is the most investigated category of side-channel attacks. The four code words of the 1-of-4 codes, namely (0001, 0010, 1000, and 0100), are split into two sets: set-0 and set-1. Using a select signal, the data processed in hardware is switched between the two encoding sets alternately such that the Hamming weight and Hamming distance are equalized. As a case study, the proposed technique is validated for the NIST standard AES-128 cipher. The proposed technique resists differential power analysis performed using statistical methods, namely correlation, mutual information, difference of means, and Welch's t-test based on the Hamming weight and distance models. The experimental results show that the proposed countermeasure has an area overhead of 2.3× with no performance degradation comparatively.

• International conference on construction engineering and project management
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• 2009.05a
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• pp.196-202
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• 2009

Study from Yogyakarta earthquake reconstruction program, cast-in-place wall using fix-size formwork system (Old-CIP) has offered a good alternative for house construction. A simulation has also confirmed that this system using mortar as the main material can provide cheapest cost and lowest total man power compared to conventional wall construction technique: brick or mortar-block wall. This paper presents the new wall construction technique: full size cast-in-place wall (New-CIP). The detail of how this new technique implemented is described. In addition, considering that material and labor cost in one area is different to others, cost analysis for different resources prices and wages of three cities are taken into a simulation. The analysis is aimed to distinguish the implementation feasibility of New-CIP system compared to the four common wall systems. Finally, its implementation resistance is also discussed.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.186-189
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• 2003

This paper discussed whole concept of bluetooth baseband and studied its detail algorithm. Important blocks, access code, security and clock management, are implemented and verified to hardware and firmware according to Specification ver.1.1. Then implementation results are compared and examined. Finally, this paper suggested the efficient system implementation method. By using test board, it could confirm that suggested implementation communicated smoothly.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.123-126
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• 2001

Block filter implementation technique for uniform filter banks is uniform in this paper. By applying block filter into decimation and interpolation filters, it is shown that down and up samplers are cancelled out in respective liters. Furthermore by applying block filters into uniform filter banks, significant reduction for computational complexity is achieved since prototype filter can be shared in each channel implementation. Also, it is shown that proposed implementation is a reconfigurable structure in terms of order variation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.124-130
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• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.