• 전자공학회논문지
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• 제50권4호
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• pp.212-218
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• 2013

본 논문에서는 위상지연필터를 이용한 리니어 모터 피스톤 진폭 추정기를 구현하였다. 리니어 컴프레서가 적용된 냉장고나 에어컨의 냉각능력을 제어하기 위해서는 단위시간동안 피스톤의 움직인 거리, 즉 피스톤의 속도를 제어해야 하는데 이때 리니어 모터의 주파수나 스트로크를 조정함으로써 가능하다. 이때, 주파수를 고정하고 스트로크를 변화시키는 것이 일반적이다. 스트로크, 즉 피스톤 진폭을 정확하게 추정하는 것이 리니어 컴프레서의 동특성을 좌우하는데, 본 연구에서는 위상지연필터를 이용한 피스톤 진폭 추정기를 제안하고 성능이 우수함을 모의실험을 통해 확인하였다.

• 한국해양공학회지
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• 제25권4호
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• pp.36-41
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• 2011

In the present paper, a direct forcing/fictitious domain (DF/FD) level set method is proposed to simulate the FSI (fluid-solid interaction) in two-phase flow. The main idea is to combine the direct-forcing/fictitious domain (DF/FD) method with the level set method in the Cartesian coordinates. The DF/FD method is a non-Lagrange-multiplier version of a distributed Lagrange multiplier/fictitious domain (DLM/FD) method. This method does not sacrifice the accuracy and robustness by employing a discrete ${\delta}$ (Dirac delta) function to transfer quantities between the Eulerian nodes and Lagrangian points explicitly as the immersed boundary method. The advantages of this approach are the simple concept, easy implementation, and utilization of the original governing equation without modification. Simulations of various water-entry problems have been conducted to validate the capability and accuracy of the present method in solving the FSI in two-phase flow. Consequently, the present results are found to be in good agreement with those of previous studies.

• 전기학회논문지
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• 제57권10호
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• pp.1796-1801
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• 2008

In this paper, a new current based maximum power point tracking (CMPPT) method is proposed for a single phase photovoltaic power conditioning system and the current based MPPT modifies incremental conductance method. The current based MPPT method makes the entire control structure of the power conditioning system simple and uses an inherent current source characteristic of solar cell array. In addition, digital phase locked loop using an all pass filter is introduced to detect phase of grid voltage as well as peak voltage. Controllers about dc/dc boost converter, dc-link voltage, dc/ac inverter is designed for a coordinated operation. Furthermore, PI current control using a pseudo synchronous d-q transformation is employed for grid current control with unity power factor. 3kW prototype photovoltaic power conditioning system is built and its experimental results are given to verify the effectiveness of the proposed control schemes.

• 대한산업공학회지
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• 제43권3호
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• pp.229-237
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• 2017

Presented in this paper is a case study of constructing a smart factory for aircraft parts. The construction procedure involves four phases. First of all, its management goals are set, and layout design and simulation are carried out in the conceptual design phase. In the detail design phase, operating scenarios for each module are written out, and probable risks are analyzed by expert groups, and then requirements for developing equipments and subsystems are determined with consideration for element technologies and their integration schemes into the smart factory. In the fabrication and installation phase, system development, equipment fabrication and installation are proceeded in a separate manner, and then integrated together subsequently. In the operation and improvement phase, the factory is stabilized, sophisticated and improved constantly during real operation.

• Journal of Power Electronics
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• 제12권4호
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• pp.654-663
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• 2012

In this paper, a digital control strategy based on equivalent fundamental and odd harmonic resonators is proposed for single-phase DVRs. By using a delay block, which can be equivalent to a bank of resonators, it rejects the fundamental and odd harmonic disturbances effectively. The structure of the single closed-loop control system consists of a delay block, a proportional gain and a set of zero phase notch filters. The principle of the controller design is discussed in detail to ensure the stability of the system. Both the supply voltage and the load current feedforwards are used to improve the response speed and the ability to eliminate disturbances. The proposed controller is simple in terms of its structure and implementation. It has good performances in harmonic compensation and dynamic response. Experimental results from a 2kW DVR prototype confirm the validity of the design procedure and the effectiveness of the control strategy.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.492-498
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• 2017

In this paper, we integrate a divide-by-3 injection-locked frequency divider (ILFD) in CMOS technology with a $0.18-{\mu}m$ BiCMOS process. We propose a self-injection technique that utilizes harmonic conversion to improve the locking range, phase-noise, and input sensitivity simultaneously. The proposed self-injection technique consists of an odd-to-even harmonic converter and a feedback amplifier. This technique offers the advantage of increasing the injection efficiency at even harmonics and thus realizes the low-power implementation of an odd-order division ILFD. The measurement results using the proposed self-injection technique show that the locking range is increased by 47.8% and the phase noise is reduced by 14.7 dBc/Hz at 1-MHz offset frequency with the injection power of -12 dBm. The designed divide-by-3 ILFD occupies $0.048mm^2$ with a power consumption of 18.2-mW from a 1.8-V power supply.

• Journal of Advanced Marine Engineering and Technology
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• 제16권4호
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• pp.102-112
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• 1992

The three-phase full(6-pulse) bridge controlled rectifier is one of the most widely used types of solid-state converters in DC drive applications for higher performance. In most of the previous designs, the gate control circuits of the converter have been designed with analog method which can be easily affected by noise. Nowdays with advances of microelectronics and power electronics, microprocessor and pheripal LSIs are increasingly used for eliminating this problems. In this paper, a novel general-purpose microprocessor -based firing system and control scheme for a three-phase controlled rectifier bridge has been developed and tested. Using the phase relations between ${\Delta}$-Y transformer in power operation part, gate pulse of the converter is generated with real time process so that microprocessor may share its time to control algorithms efficiently. The firing angle of the converter is smoothly controlled in the range of 0 $^{\dirc}$ to 180$^{\dirc}$ with a fast respone and a constant open loop gain, even for the case where the converter is fed by a weak AC system of unregulated frequency. The hardware and software control circuit implementation built around a 80286 microprocessor is discussed, and the experimental results are given. This scheme uses less hardware components and has higher dynamic performance in variable speed DC drive applications.

• International journal of advanced smart convergence
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• 제9권1호
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• pp.172-176
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• 2020

The implementation of a low phase noise voltage controlled oscillator (VCO) is important for the signal integrity of wireless communication terminal. A low phase noise wideband VCO for a wireless local area network (WLAN) application is presented in this paper. A 6-bit coarse tune capacitor bank (capbank) and a fine tune varactor are used in the VCO to cover the target band. The simulated oscillation frequency tuning range is from 8.6 to 11.6 GHz. The proposed VCO is desgned using 65 nm CMOS technology with a high quality (Q) factor bondwire inductor. The VCO is biased with 1.8 V VDD and shows 9.7 mA current consumption. The VCO exhibits a phase noise of -122.77 and -111.14 dBc/Hz at 1 MHz offset from 8.6 and 11.6 GHz carrier frequency, respectively. The calculated figure of merit(FOM) is -189 dBC/Hz at 1 MHz offset from 8.6 GHz carrier. The simulated results show that the proposed VCO performance satisfies the required specification of WLAN standard.

• 한국항행학회논문지
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• 제14권5호
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• pp.640-647
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• 2010

최근 많은 연구자들에 의하여 위성항법 측정값 중 반송파 측정값에 대한 고장검출 연구가 진행되어 왔으나, 육상교통 환경에서의 적용연구는 활발히 진행되지 않았다. 본 논문에서는 움직이는 물체의 동적특성과 복수의 위성항법 수신기 사이의 기준 거리 제한 조건을 활용하여 위성항법 반송파 측정값의 고장검출을 수행하였다. 반송파 측정값의 고장은 다중경로 등을 포함하고 있으며 측정값 영역에서 고장검출을 수행함으로써 위치결정을 수반하는 기존의 고장검출 방법에 비하여 그 구현이 용이함을 확인하였다.

• 한국통신학회논문지
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• 제14권4호
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• pp.338-347
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• 1989

본 논문에서는 종래의 위상누적방식을 이용한 디지털 주파수합성기의 성능을 향상시키기 위해, 클럭주파수합성방식의 디지털 주파수합성기를 설계하고 제작하였다. 고정된 시스템 클럭주파수를 가지고 위상초기치를 가변, 누적시키는 위상 누적방식과는 달리, 클럭주파수 합성방식에서는 PLL을 사용하여 클럭주파수를 가변합성하였고, 이를 N진 계수기의 입력으로 사용하여 고정된 위상 누적치를 갖게 하였다. 성능실험결과 기존의 위상누적방식에서 나타났던 주기적인 출력왜곡현상이 발생하지 않게되어,양자화 불요잠음의 발생이 줄어들었으나, 위상누적방식보다 동일한 설계조건에서 출력대역폭이 계수기의 계수상태에 반비례하여 좁아졌고, PLL을 사용하기 때문에 회로구성이 복잡해졌다.