• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.212-218
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• 2013

In this paper, a linear motor piston amplitude estimator using phase lag filter has been implemented. In order to control the cooling capability of a refrigerator or an air conditioner in which liner compressors are applied, the piston speed should be controlled. The piston speed control can be obtained by adjusting the frequency or the stroke of linear motors. The dynamic performance of linear compressors depends on how accurately the stroke or the piston amplitude is estimated. A linear motor piston amplitude estimator using phase lag filter is proposed and the superior performance of our estimator is verified via some simulation studies.

• Journal of Ocean Engineering and Technology
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• v.25 no.4
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• pp.36-41
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• 2011

In the present paper, a direct forcing/fictitious domain (DF/FD) level set method is proposed to simulate the FSI (fluid-solid interaction) in two-phase flow. The main idea is to combine the direct-forcing/fictitious domain (DF/FD) method with the level set method in the Cartesian coordinates. The DF/FD method is a non-Lagrange-multiplier version of a distributed Lagrange multiplier/fictitious domain (DLM/FD) method. This method does not sacrifice the accuracy and robustness by employing a discrete ${\delta}$ (Dirac delta) function to transfer quantities between the Eulerian nodes and Lagrangian points explicitly as the immersed boundary method. The advantages of this approach are the simple concept, easy implementation, and utilization of the original governing equation without modification. Simulations of various water-entry problems have been conducted to validate the capability and accuracy of the present method in solving the FSI in two-phase flow. Consequently, the present results are found to be in good agreement with those of previous studies.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.10
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• pp.1796-1801
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• 2008

In this paper, a new current based maximum power point tracking (CMPPT) method is proposed for a single phase photovoltaic power conditioning system and the current based MPPT modifies incremental conductance method. The current based MPPT method makes the entire control structure of the power conditioning system simple and uses an inherent current source characteristic of solar cell array. In addition, digital phase locked loop using an all pass filter is introduced to detect phase of grid voltage as well as peak voltage. Controllers about dc/dc boost converter, dc-link voltage, dc/ac inverter is designed for a coordinated operation. Furthermore, PI current control using a pseudo synchronous d-q transformation is employed for grid current control with unity power factor. 3kW prototype photovoltaic power conditioning system is built and its experimental results are given to verify the effectiveness of the proposed control schemes.

• Journal of Korean Institute of Industrial Engineers
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• v.43 no.3
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• pp.229-237
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• 2017

Presented in this paper is a case study of constructing a smart factory for aircraft parts. The construction procedure involves four phases. First of all, its management goals are set, and layout design and simulation are carried out in the conceptual design phase. In the detail design phase, operating scenarios for each module are written out, and probable risks are analyzed by expert groups, and then requirements for developing equipments and subsystems are determined with consideration for element technologies and their integration schemes into the smart factory. In the fabrication and installation phase, system development, equipment fabrication and installation are proceeded in a separate manner, and then integrated together subsequently. In the operation and improvement phase, the factory is stabilized, sophisticated and improved constantly during real operation.

• Journal of Power Electronics
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• v.12 no.4
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• pp.654-663
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• 2012

In this paper, a digital control strategy based on equivalent fundamental and odd harmonic resonators is proposed for single-phase DVRs. By using a delay block, which can be equivalent to a bank of resonators, it rejects the fundamental and odd harmonic disturbances effectively. The structure of the single closed-loop control system consists of a delay block, a proportional gain and a set of zero phase notch filters. The principle of the controller design is discussed in detail to ensure the stability of the system. Both the supply voltage and the load current feedforwards are used to improve the response speed and the ability to eliminate disturbances. The proposed controller is simple in terms of its structure and implementation. It has good performances in harmonic compensation and dynamic response. Experimental results from a 2kW DVR prototype confirm the validity of the design procedure and the effectiveness of the control strategy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.492-498
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• 2017

In this paper, we integrate a divide-by-3 injection-locked frequency divider (ILFD) in CMOS technology with a $0.18-{\mu}m$ BiCMOS process. We propose a self-injection technique that utilizes harmonic conversion to improve the locking range, phase-noise, and input sensitivity simultaneously. The proposed self-injection technique consists of an odd-to-even harmonic converter and a feedback amplifier. This technique offers the advantage of increasing the injection efficiency at even harmonics and thus realizes the low-power implementation of an odd-order division ILFD. The measurement results using the proposed self-injection technique show that the locking range is increased by 47.8% and the phase noise is reduced by 14.7 dBc/Hz at 1-MHz offset frequency with the injection power of -12 dBm. The designed divide-by-3 ILFD occupies $0.048mm^2$ with a power consumption of 18.2-mW from a 1.8-V power supply.

• Journal of Advanced Marine Engineering and Technology
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• v.16 no.4
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• pp.102-112
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• 1992

The three-phase full(6-pulse) bridge controlled rectifier is one of the most widely used types of solid-state converters in DC drive applications for higher performance. In most of the previous designs, the gate control circuits of the converter have been designed with analog method which can be easily affected by noise. Nowdays with advances of microelectronics and power electronics, microprocessor and pheripal LSIs are increasingly used for eliminating this problems. In this paper, a novel general-purpose microprocessor -based firing system and control scheme for a three-phase controlled rectifier bridge has been developed and tested. Using the phase relations between ${\Delta}$-Y transformer in power operation part, gate pulse of the converter is generated with real time process so that microprocessor may share its time to control algorithms efficiently. The firing angle of the converter is smoothly controlled in the range of 0 $^{\dirc}$ to 180$^{\dirc}$ with a fast respone and a constant open loop gain, even for the case where the converter is fed by a weak AC system of unregulated frequency. The hardware and software control circuit implementation built around a 80286 microprocessor is discussed, and the experimental results are given. This scheme uses less hardware components and has higher dynamic performance in variable speed DC drive applications.

• International journal of advanced smart convergence
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• v.9 no.1
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• pp.172-176
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• 2020

The implementation of a low phase noise voltage controlled oscillator (VCO) is important for the signal integrity of wireless communication terminal. A low phase noise wideband VCO for a wireless local area network (WLAN) application is presented in this paper. A 6-bit coarse tune capacitor bank (capbank) and a fine tune varactor are used in the VCO to cover the target band. The simulated oscillation frequency tuning range is from 8.6 to 11.6 GHz. The proposed VCO is desgned using 65 nm CMOS technology with a high quality (Q) factor bondwire inductor. The VCO is biased with 1.8 V VDD and shows 9.7 mA current consumption. The VCO exhibits a phase noise of -122.77 and -111.14 dBc/Hz at 1 MHz offset from 8.6 and 11.6 GHz carrier frequency, respectively. The calculated figure of merit(FOM) is -189 dBC/Hz at 1 MHz offset from 8.6 GHz carrier. The simulated results show that the proposed VCO performance satisfies the required specification of WLAN standard.

• Journal of Advanced Navigation Technology
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• v.14 no.5
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• pp.640-647
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• 2010

Many methods have been proposed to detect faults of carrier phase measurements, but there are no distinguished methods for land transportation systems. in this paper, the baseline constraints are used to detect faults in GPS carrier phase measurements with vehicle dynamic information. The faults include the multipath on GPS carrier measurements. Multiple antenna groups are used for this research. In the measurement domain the fault detection has been accomplished so that the implementation is easier than other methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.338-347
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• 1989

In this paper, the digital frequency synthesizer with the clock ccunting method is designed and implemented to increase the performace of the digital frequency synthesizer with pahse accumulating method which was developed before. Unlike an phase accumulating method, clock countind method is supplied a continually changeable clock frequency with PLL(Phase Locked Loop) and allocated a fixed phase step with N-ary counter. Form the experimenta results, it is confirmed that any periodic distorition phenomena are disappeared, and truncation harmonics are more reduced. But the output bandwidths are decreased in inverse proportion to the counter counting number and the circuits are somewhat complex than phase accumulating method.