• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.39-44
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• 2008

Scan architecture is very effective design-for-testability technique that is widely used for high testability, however, it requires so much test time due to test vector shifting time. In this paper, an efficient scan test method is presented that is based on the Illinois scan architecture. The proposed method maximizes the common input effect via a scan chain selection scheme. Experimental results show the proposed method requires very short test time and small data volume by increasing the efficiency of common input effect.