• Title/Summary/Keyword: IUAN

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WSN Lifetime Analysis: Intelligent UAV and Arc Selection Algorithm for Energy Conservation in Isolated Wireless Sensor Networks

  • Perumal, P.Shunmuga;Uthariaraj, V.Rhymend;Christo, V.R.Elgin
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.9 no.3
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    • pp.901-920
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    • 2015
  • Wireless Sensor Networks (WSNs) are widely used in geographically isolated applications like military border area monitoring, battle field surveillance, forest fire detection systems, etc. Uninterrupted power supply is not possible in isolated locations and hence sensor nodes live on their own battery power. Localization of sensor nodes in isolated locations is important to identify the location of event for further actions. Existing localization algorithms consume more energy at sensor nodes for computation and communication thereby reduce the lifetime of entire WSNs. Existing approaches also suffer with less localization coverage and localization accuracy. The objective of the proposed work is to increase the lifetime of WSNs while increasing the localization coverage and localization accuracy. A novel intelligent unmanned aerial vehicle anchor node (IUAN) is proposed to reduce the communication cost at sensor nodes during localization. Further, the localization computation cost is reduced at each sensor node by the proposed intelligent arc selection (IAS) algorithm. IUANs construct the location-distance messages (LDMs) for sensor nodes deployed in isolated locations and reach the Control Station (CS). Further, the CS aggregates the LDMs from different IUANs and computes the position of sensor nodes using IAS algorithm. The life time of WSN is analyzed in this paper to prove the efficiency of the proposed localization approach. The proposed localization approach considerably extends the lifetime of WSNs, localization coverage and localization accuracy in isolated environments.

Robust Parameter Design via Taguchi's Approach and Neural Network

  • Tsai, Jeh-Hsin;Lu, Iuan-Yuan
    • International Journal of Quality Innovation
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    • v.6 no.1
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    • pp.109-118
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    • 2005
  • The parameter design is the most emphasized measure by researchers for a new products development. It is critical for makers to achieve simultaneously in both the time-to-market production and the quality enhancement. However, there are difficulties in practical application, such as (1) complexity and nonlinear relationships co-existed among the system's inputs, outputs and control parameters, (2) interactions occurred among parameters, (3) where the adjustment factors of Taguchi's two-phase optimization procedure cannot be sure to exist in practice, and (4) for some reasons, the data became lost or were never available. For these incomplete data, the Taguchi methods cannot treat them well. Neural networks have a learning capability of fault tolerance and model free characteristics. These characteristics support the neural networks as a competitive tool in processing multivariable input-output implementation. The successful fields include diagnostics, robotics, scheduling, decision-making, prediction, etc. This research is a case study of spherical annealing model. In the beginning, an original model is used to pre-fix a model of parameter design. Then neural networks are introduced to achieve another model. Study results showed both of them could perform the highest spherical level of quality.

A CMOS 5-bit 5GSample/Sec Analog-to-digital Converter in 0.13um CMOS

  • Wang, I-Hsin;Liu, Shen-Iuan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.1
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    • pp.28-35
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    • 2007
  • This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in $0.13{\mu}m$ 1P8M CMOS process and the total power consumption is 113mW with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200MHz at 5-GSample/sec.