• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.8
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• pp.30-41
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• 2001

In this paper, the architecture of Dynamic GSMP V3(General Switch Management Protocol Version 3), an open interface protocol with resource management functions for efficient IP service on ATM over MPLS, is proposed and implemented in hardware. And we compare and analyze the proposed GSMP with the GSMP under standardization process in terms of CLR (Cell Loss Rate). We design the Slave block of the Dynamic GSMP V3 using SAM-SUNG SoG $0.5{\mu}m$ process, which performs functions for switch connection control in the ATM Switch. In order to compare difference performanaces between the proposed method and the conventional one, we conducts simulations using the minimum buffer search algorithm with random cell generation. The exponential results show that the proposed method leads to performance enhancement in CLR.

• Journal of the Korea Society of Computer and Information
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• v.13 no.2
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• pp.143-151
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• 2008

74% of Internet users use the UCC, and You Tube using firearms in a crime occurred. Internet crime occurred in the online, non-face transaction, anonymous, encapsulation. In this paper, we are studied a Network Forensic Way and a technique analyze an aspect criminal the Internet haying appeared at Internet UCC, and to chase. Study ID, IP back-tracking and position chase through corroborative facts collections of the UCC which used UCC search way study of the police and a public prosecutor and storage way and network forensic related to crimes of Internet UCC. Proof data encrypt, and store, and study through approach control and user authentication so that they are adopted to legal proof data through integrity verification after transmission and storages. This research via the Internet and criminal conspiracy to block the advance promotion, and for the criminal investigative agencies of the Internet will contribute to the advancement forensics research.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.4
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• pp.35-42
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• 2010

This paper reviews the current studies about the current secure OS, security module and SELinux, and suggests Linux access control module that uses the user discriminating authentication, security authority inheritance of subjects and objects, reference monitor and MAC class process and real-time audit trailing using DB. First, during the user authentication process, it distinguishes the access permission IP and separates the superuser(root)'s authority from that of the security manager by making the users input the security level and the protection category. Second, when the subjects have access to the objects through security authority inheritance of subjects and objects, the suggested system carries out the access control by comparing the security information of the subjects with that of the objects. Third, this system implements a Reference Monitor audit on every current events happening in the kernel. As it decides the access permission after checking the current MAC security attributes, it can block any malicious intrusion in advance. Fourth, through the real-time audit trailing system, it detects all activities in the operating system, records them in the database and offers the security manager with the related security audit data in real-time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1332-1340
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• 2007

This paper describes an efficient hardware design of key wrap/unwrap algorithm for security layer of WiBro system. The key wrap/unwrap core (WB_KeyWuW) is based on AES (Advanced Encryption Standard) algorithm, and performs encryption/decryption of 128bit TEK (Traffic Encryption Key) with 128bit KEK (Key Encryption Key). In order to achieve m area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented by using field transformation technique. As a result, the gate count of the WB_KeyWuW core is reduced by about 25% compared with conventional LUT (Lookup Table)-based design. The WB_KeyWuW con designed in Verilog-HDL has about 14,300 gates, and the estimated throughput is about $16{\sim}22-Mbps$ at 100-MHz@3.3V, thus the designed core can be used as an IP for the hardware design of WiBro security system.

• Journal of the Korea Society of Computer and Information
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• v.18 no.8
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• pp.95-104
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• 2013

DDoS attacks have became as a social threat since 2009 7.7 DDoS turmoil. Even though defence techniques have been developing to provide against those threats, they become much more sophisticate. In recent years, the attack form of DDoS is changing from high amount of traffic attack of network layers to highly sophisticate small amount of application layers. To make matters worse, attack agent for the attack has became very intelligent so that it is difficult to be blocked since it can't be distinguished from normal PCs. In the user authentication system(such as CAPTCHA) User intervention is required to distinguish normal PCs and intelligent attack agents and in particular, in a NAT environment, IP-based blocking method can be cut off the normal users traffic at the same time. This research examined defense techniques which are able to distinguish between agent and normal PC and effectively block ways the HTTP DDoS offense applying one-time session key based authentication method using Cookie which is used in HTTP protocol to protect web sever from sophisticate application layer of DDoS.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.97-107
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• 2004

This paper presents an System-on-Chip(SoC) implementation of fingerprint feature extraction system. Typical fingerprint feature extraction systems employ binarization and thinning processes which cause many extraction errors for low qualify fingerprint images and degrade the accuracy of the entire fingerprint recognition system. To solve these problems, an algorithm directly following ridgelines without the binarization and thinning process has been proposed. However, the computational requirement of the algorithm makes it hard to implement it on SoCs by using software only. This paper presents an implementation of the ridge-following algorithm onto SoCs. The algorithm has been modified to increase the efficiency of hardwares. Each function block of the algorithm has been implemented in hardware or in software by considering its computational complexity, cost and utilization of the hardware, and efficiency of the entire system. The fingerprint feature extraction system has been developed as an IP for SoCs, hence it can be used on many kinds of SoCs for smart cards.

• Geophysics and Geophysical Exploration
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• v.24 no.4
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• pp.171-179
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• 2021

We outline a process for estimating Cole-Cole parameters from time-domain induced polarization (IP) data. The IP transients are all inverted to 2D Cole-Cole earth models that include resistivity, chargeability, relaxation time, and the frequency exponent. Our inversion algorithm consists of two stages. We first convert the measured voltage decay curves into time series of current-on time apparent resistivity to circumvent the negative chargeability problem. As a first step, a 4D inversion recovers the resistivity model at each time channel that increases monotonically with time. The desired intrinsic Cole-Cole parameters are then recovered by inverting the resistivity time series of each inversion block. In the second step, the Cole-Cole parameters can be estimated readily by setting the initial model close to the true value through a grid search method. Finally, through inversion procedures applied to synthetic data sets, we demonstrate that our algorithm can image the Cole-Cole earth models effectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.5
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• pp.491-498
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• 2016

An ACL(: Access List), a list that determines network access, is used for the security of the network. An ACL if applied to a interface of router can filter particular packets. Also it can block or allow the access of certain unauthorized IPs or ports, based on the source address, destination address, and TCP/UDP port. This paper presents a simulation case to verify the effect of a router-based network applying Standard ACL or Extended ACL. The network was created through designing topology and then making a common virtual network using a Packet Tracer.