• The Magazine of the IEIE
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• v.30 no.9
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• pp.965-975
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• 2003

여러기능들이 복합적으로 통합되고 있는 단일칩시스템을 설계하는데 있어 소프트웨어와 하드웨어를 가능한 일찍 통합하여 검증하는 것이 무엇보다 중요하다. 이러한 조기 통합검증에 필요한 것이 가상프로토타입(Virtual-Prototype) 이다. 본 고에서는 IP(Intellectual Property) 와 단일칩시스템(SoC : System-on-a-Chip) 설계 및 검증에서 가상프로토타입의 필요성과 역할 그리고 이에 관련된 기술들에 대해 정리하고, 프로세싱 코어가 있는 단일칩시스템을 SystemC로 가상프로토타이핑한 사례를 통해 그 유용성을 설명한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.1089-1094
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• 2000

소형 고성능 가전기기를 실현하기 위한 다기능 고집적의 실리콘화에 대응하기 위하여 반도체 업계는 SoC(System On a Chip) 설계, 반도체 지적 재산권인 IP(Intellectual Property)에 관한 연구를 두개의 핵심 연구 항목으로 설정하여 진행되어 왔다. 반도체 레이아웃 이식 자동화 시스템은 설계 재활용(Design Reuse), IP의 실용화와 확산을 위한 핵심 연구 과제 중의 하나로써, Time-To-Market 과 Time-To-Money 를 동시에 가능토록 하는 근간의 기술이 된다. 본 연구는 정확하고 고속의 IP내의 반도체 소자 인식 알고리즘, 그래프를 이용한 제한 조건의 구현과 해석, 향상된 컴팩션(Compaction) 알고리즘의 연구로 말미암아 기존의 연구 결과 대비 평균 20배의 속도 향상과 평균 41%의 메모리만을 사용함으로써 경쟁 기술 대비 월등한 우위를 보이고 있다. 이로써, 대형의 반도체 설계 도면의 처리를 가능하도록 하였으며, 반도체 IP의 응용성(flexibility)을 부여 함으로써, IP의 재활용의 기초 연구와 SoC 설계 확산에 지렛대 역할을 하는 연구가 되리라고 예측한다.

• Journal of the Korea Society of Computer and Information
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• v.23 no.1
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• pp.33-39
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• 2018

In this paper, We studied the possibility of SoC(System On Chip) design using infrared image processing IP(Intellectual Property). And, we studied NUC(Non Uniformity Correction), BPR(Bad Pixel Recovery), and CEM(Contrast Enhancement) processing, the infrared image processing algorithm implemented by IP. We showed the logic and timing diagram implemented through the hardware block designed based on each algorithm. Each algorithm was coded as RTL(Register Transfer Level) using Verilog HDL(Hardware Description Language), ALTERA QUARTUS synthesis, and programed in FPGA(Field Programmable Gated Array). In addition, we have verified that the image data is processed at each algorithm without any problems by integrating the infrared image processing algorithm. Particularly, using the directly manufactured electronic board, Processor, SRAM, and FLASH are interconnected and tested and the verification result is presented so that the SoC type can be realized later. The infrared image processing IP proposed and verified in this study is expected to be of high value in the future SoC semiconductor fabrication. In addition, we have laid the basis for future application in the camera SoC industry.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.6 no.1
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• pp.133-158
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• 2011

In 2030s, as we enter in to the era of BT (Bio-Technology) market opening up, technologies in all areas such as IT, data analysis, IC and biochemistry are necessitated. New development in technology will be based on "Convergence", especially between IT and BT. In order to have synergy effects from the convergence, those related industries and universities should be physically inter-related in an appropriate location. Until 2009, 819 industrial clusters where many Korean industries and firms are concentrated have been constructed in Korea. They have had supports from various institutions and facilities. However, few systems designed to assist "intellectual property (IP) service" for technology convergence are found in Korea. Thus, by analyzing current problems and challenges of the Korean industrial clusters, this paper suggests a possible answer to maximize the synergy from technology convergence through organic cooperation among companies in industrial clusters. This paper finds that the Korean industrial clusters need to establish IP service supporting center while suggesting its function and concept on organization structure, and work flow, which help firms to develop IP strategies. In addition, the paper provides a direction for current IP system and policies implemented by the Korean government to be more effective to small-and-medium-sized companies located in the industrial clusters.

• Journal of Digital Convergence
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• v.14 no.3
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• pp.227-234
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• 2016

This study compares and analyzes the national competitiveness in IP finance using the diamond model. The main findings of our analysis are as follows. First, assuming Korea's competitiveness in IP finance to be 1, USA with 1.63 has the highest competitiveness of all countries compared, and Israel is 1.49 followed by Japan with 1.37. Second, Korea and other countries compared show large differences in the areas of demand conditions, strategic structure, and competition. Third, Korea is inferior compared to other countries considered in terms of the factors including the protection of investors and IPR, and government policies. Since most of the factors in which Korea shows inferiority can be managed by public policies, to strengthen the competitiveness of IP finance, the government's active support to build industrial foundation are required.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.167-173
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• 2015

This paper presents a study on the Full-HD HEVC(High Efficiency Video Coding) encoder IP(Intellectual Property) design. The designed IP is for HEVC main profile 4.1, and performs encoding with a speed of 60 fps of full high definition. Before hardware and software design, overall reference model was developed with C language, and we proposed a parallel processing architecture for low-power consumption. And also we coded firmware and driver programs relating IP. The platform for verification of developed IP was developed, and we verified function and performance for various pictures under several encoding conditions by implementing designed IP to FPGA board. Compared to HM-13.0, about 35% decrease in bit-rate under same PSNR was achieved, and about 25% decrease in power consumption under low-power mode was performed.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.10
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• pp.467-473
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• 2007

Power-aware design is one of the most important areas to be emphasized in multimedia mobile systems, in which data transfers dominate the power consumption. In this paper, we propose a new architecture for motion compensation (MC) of H.264/AVC with power reduction by decreasing the data transfers. For this purpose, a reconfigurable microarchitecture based on data type is proposed for interpolation and it is mapped onto the dedicated motion compensation IP (intellectual property) effectively without sacrificing the performance or the system latency. The original quarter-pel interpolation equation that consists of one or two half-pel interpolations and one averaging operation is designed to have different execution control modes, which result in decreasing memory accesses greatly and maintaining the system efficiency. The simulation result shows that the proposed method could reduce up to 87% of power consumption caused by data transfers over the conventional method in MC module.

• The Journal of the Korea Contents Association
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• v.15 no.10
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• pp.447-456
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• 2015

In this paper a new model of storytelling related to patent in the field of business as a sort of Intellectual Property(IP) was proposed. The patent related storytelling is investigated in the view points of variety of customers, purposes and applications which is different from the conventional OSMU, transmedia or crossmedia storytelling. In business there are several stages related to patent such as the initial conceptualization and development of technology, apply for and registration of patent, legal conflict like patent invalidation trial and action for infringement of patent and damages, and the commercialization stage like development of product based on patent, advertisement and marketing. Multiple sources optimized to the purpose in each stage of patent related business as well as to multiple convergence application of a patent. Similarly, multi-use refers to the fact that storytelling can be applied in each stage of patent oriented business. The effectiveness and usefulness of proposed MSMU model is also investigated.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.175-181
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• 2015

In this paper, we develop a 2.4GHz ISM band wireless communication platform prototype based on embedded linux which support can be u-Hospital service. The developed system is available connecting between ARM920T processor board and FPGA board and linking IEEE 802.11b PHY board, AD/DA(10Bit) and RF(2.4GHz) board for wireless access. It is also can be utilized for the embedded system design with IEEE 802.11b/g Access Point(Option: IEEE 802.11a/b/g) test due to the Embedded Linux. Also, the developed system is possible to test and verify the radio access technology, Modem(OFDM etc) and IP(Intellectual Property) circuit. And make the most use of the system, we search for a expansion to that home and mobile healthcare, wellness service application.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.293-304
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• 2011

In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.