• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.12
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• pp.1065-1072
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• 2014

We developed a GPS digital signal processing FPGA IP, SIGP-1001 to replace the obsolete GP2021 device, which has been used for many space-borne GPS receivers. From a series of tests, we verified that SIGP-1001 has equivalent performance to the GP2021 device under the same operating condition and concluded that SIGP-1001 can replace the GP2021 device. The reliability of a GPS receiver can be improved by using a space-grade FPGA with SIGP-1001 instead of the GP2021 device and its performance is expected to be improved by increasing the number of search channels.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.34-44
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• 2006

A system-on-a-chip (SoC) design uses pre-verified IP hardware blocks in order to reduce design time. We need interface circuits to connect IPs with different protocols. In SoC design we should design interface circuits frequently and these tasks are somewhat time-consuming and error-prone. So it is necessary to generate the interface circuits automatically. Several studies have been made on generating interface circuits only from the communication protocols of IPs. With existing approaches, it is not easy to generate interface circuits connecting two IPs only from communication protocols: connection between IP with address and W without address, connection between IP with only one port to transfer address/data and IP with different ports for address and data connection between IP that transfer address and data together and IP that transfer only one address with a number of data in a burst. No consideration of various characteristics of IPs and no changed algorithm are responsible for it. In order to solve this problem, the proposed approach categorizes communication protocols of IPs, and takes characteristics matching of IPs into account during the interface synthesis. In experiments, we show that we could correctly generate and verify interface circuits for IPs with different characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.182-192
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• 2010

This paper proposes the hardware IP design of JBIG2 encoder. In order to facilitate the next generation FAX after the standardization of JBIG2, major modules of JBIG2 encoder are designed and implemented, such as symbol extraction module, Huffman coder, MMR coder, and MQ coder. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the synthesis of VHDL code. To minimize the memory usage, 128 lines of input image are processed succesively instead of total image. The synthesized IPs are downloaded to Virtex-4 FX60 FPGA on ML410 development board. The four synthesized IPs utilize 36.7% of total slice of FPGA. Using Active-HDL tool, the generated IPs were verified showing normal operation. Compared with the software operation using microblaze cpu on ML410 board, the synthesized IPs are better in operation time. The improvement ratio of operation time between the synthesized IP and software is 17 times in case of symbol extraction IP, and 10 times in Huffman coder IP. MMR coder IP shows 6 times faster and MQ coder IP shows 2.2 times faster than software only operation. The synthesized H/W IP and S/W module cooperated to succeed in compressing the CCITT standard document.

• Journal of Korean Society for Quality Management
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• v.42 no.3
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• pp.477-496
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• 2014

Purpose: This paper has examined the impact of open innovation business model in technology commercialization with the data from 30 companies of manufacturing firms in South Korea. Methods: The findings provide support for distinguishing five hypotheses relating to development time, IP management, sales, firm size and R&D intensity. To test the hypotheses, data were collected using via e-mail and fax. Small and medium-sized (less than 300 employees) and large industrial firms were chosen for this study. Results: The result shows that openness in its business model is positively associated with successful technology commercialization. Conclusion: The major findings and the implications are: First, as the business model gets more open, development period of technology will be more favorable which gets benefit from rising costs of innovation. Second, as the business model gets more open, large portion of sales are created from new products. Thus, the problem of shorter product life in the market which affects large portion of market revenue can be solved through an open business model. Third, in general, R&D intensity, firm size and the level of IP management affect determination of business model types. The findings also suggest that companies need to increasingly address their external technology exploitation process instead of focusing on their internal innovation processes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1323-1332
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• 2005

EAP (Extensible authentication protocol) is a sort of general framework for authentication rather than a specific authentication protocol. An important consequence of this is that EAP can accommodate a variety of authentication/key-establishment protocols for different internet access networks possibly integrated to a common IP core network This paper tries a comparative analysis of several specific authentication/key establishment protocols for EAP, and suggest a strategic viewpoint toward the question: which one to un. In addition, we tried to make things clear about an intellectual property right issue with regard to some password-based protocols.

• Journal of Digital Convergence
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• v.14 no.3
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• pp.83-94
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• 2016

The objective of this paper is to examine the determinants of technology transfer for Small and Medium Enterprises. Based on IP-MARKET, KIPRIS, and Wintelips, we employ the logistic regression analysis using all data related with technology transfer in markets for intellectual property rights from 2008 through 2012. Our main results are as followings: (i)the more inventors the higher possibility; and (ii)the more claims and forwards the higher possibility of success in technology transfer in Small and Medium Enterprises.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.62-65
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• 2011

FPGA는 대용량의 게이트를 지원하는 하드웨어를 프로그램 할 수 있는 디바이스이다. ASIC을 위해 설계된 로직은 칩으로 제조되기 전에 검증 과정을 거친다. 이 검증 과정에서 시뮬레이션의 한계를 극복하기 위해 FPGA를 사용한 에뮬레이션 방법을 많이 채택한다. 에뮬레이션 과정에서 ASIC의 동작 속도로 검증하는 것이 바람직하지만 FPGA의 특성상 ASIC과 같은 속도로 동작하기는 쉽지 않은 것이 현실이다. 본 논문에서는 HDL 코딩 방법에 따른 FPGA의 성능 민감도를 실험하였다. 실험 및 평가를 위해 다양한 알고리즘을 가진 가산기를 이용하였고 각 가산기 종류와 비트수에 따라 Verilog-HDL을 이용하여 코딩하였으며 대표적인 FPGA 제조사(Altera와 Xilinx)별, 디바이스별로 동작 속도와 자원 사용량을 측정하였다. 실험 결과 FPGA 제조사별로 다른 경향을 보임을 확인하였다. 성능 면에서는 비트별로 다소 차이는 있지만 Altera 디바이스에서는 Ripple Carry, Carry Lookahead 가산기보다 Prefix 가산기의 성능이 우수하게 나왔다. Xilinx 디바이스에서는 예상과 달리 가산기들 사이의 성능 차이가 크게 나지 않았으며 Ripple Carry, Carry Lookahead 가산기가 Prefix 가산기보다 높은 성능을 보이는 경우도 있었다. 비용 면에서는 디바이스별로 큰 차이가 나지 않았으며 ASIC과 비슷한 성능 민감도를 보였다. 그리고 각 제조사에서 제공하는 IP(Intellectual Property) Core를 사용했을 경우는 대부분의 디바이스에서 우수한 성능을 보여 주었다. TSMC 90nm 공정 기술로 제작한 ASIC과 IP Core를 비교했을 때는 ASIC의 성능이 4배 정도 우수한 것으로 나타났다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2365-2373
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• 2011

This paper propose the hardware IP of real-time face detection system for mobile devices and digital cameras required for high speed, smaller size and lower power. The proposed face detection system is robust against illumination changes, face size, and various face angles as the main cause of the face detection performance. Input image is transformed to LBP(Local Binary Pattern) image to obtain face characteristics robust against illumination changes, and detected the face using face feature data that was adopted to learn and generate in the various face angles using the Adaboost algorithm. The proposed face detection system can be detected maximum 36 faces at the input image size of QVGA($320{\times}240$), and designed by Verilog-HDL. Also, it was verified hardware implementation by using Virtex5 XC5VLX330 FPGA board and HD CMOS image sensor(CIS) for FPGA verification.

• Journal of Korea Game Society
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• v.16 no.5
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• pp.159-168
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• 2016

$Pok{\acute{e}}mon$ Go is an augmented reality (AR) game developed jointly by Niantic and Nintendo. It's a new type of augmented reality role-playing game (RPG) where AR elements like location information, visual recognition technology and GPS navigation technology are integrated with the intellectual property of the popular $Pok{\acute{e}}mon$ anime. The global success of $Pok{\acute{e}}mon$ Go can be attributed to the innovative incorporation of AR technologies into the game but also to the utilization of the Pokemon story which had been developed for 20 years. In summary, Pokemon Go is the fruitful result of a successful storytelling that combines the humanistic imagination of a popular, cultural archetype and the engineering imagination of AR game technologies.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.659-662
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• 2005

A parameterized FFT/IFFT core generator (PFFT_CoreGen) is designed, which can be used as an essential IP (Intellectual Property) in various OFDM modem designs. The PFFT_CoreGen generates Verilog-HDL models of FFT cores in the range of 64 ${\sim}$ 2048-point. To optimize the performance of the generated FFT cores, the PFFT_CoreGen can select the word-length of input data, internal data and twiddle factors in the range of 8-b ${\sim}$ 24-b. Some design techniques for low-power design are considered from algorithm level to circuit level.