• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.935-938
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• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

• Transactions on Electrical and Electronic Materials
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• v.8 no.2
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• pp.53-57
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• 2007

In this study, a novel slurry containing ceria as the abrasive particles was analyzed in terms of its frictional, thermal and kinetic attributes for interlayer dielectric (ILD) CMP application. The novel slurry was used to polish 200-mm blanket ILD wafers on an $IC1000_{TM}$ K-groove pad with in-situ conditioning. Polishing pressures ranged from 1 to 5 PSI and the sliding velocity ranged from 0.5 to 1.5 m/s. Shear force and pad temperature were measured in real time during the polishing process. The frictional analysis indicated that boundary lubrication was the dominant tribological mechanism. The measured average pad leading edge temperature increased from 26.4 to $38.4\;^{\circ}C$ with the increase in polishing power. The ILD removal rate also increased with the polishing power, ranging from 400 to 4000 A/min. The ILD removal rate deviated from Prestonian behavior at the highest $p{\times}V$ polishing condition and exhibited a strong correlation with the measured average pad leading edge temperature. A modified two-step Langmuir-Hinshelwood kinetic model was used to simulate the ILD removal rate. In this model, transient flash heating temperature is assumed to dominate the chemical reaction temperature. The model successfully captured the variable removal rate behavior at the highest $p{\times}V$ polishing condition and indicates that the polishing process was mechanical limited in the low $p{\times}V$ polishing region and became chemically and mechanically balanced with increasing polishing power.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.119-120
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• 2008

ILD CMP process has been well accepted for the planarization of the dielectric oxide film and becomes a critical process in ULSI manufacturing due to the rapid shrinkage of the design rule for the device. In total manufacturing process steps for a device, the proportion of ILD CMP process has been gradually increased. Ever since ILD CMP has been introduced, the scratches have been a major defects on polished surfaces which cause the electrical shorts between vias or metal lines [1,2]. It was reported that micro-scratches are caused by large, irregularly shaped particles during CMP process. Therefore, most of the CMP users have used < 5 m POU filter to remove and reduce the scratch source from the slurry. However, the scratch has always been the biggest concern in ILD polishing whatever preventive actions are taken. Silica and ceria slurries are widely used for ILD CMP process. There are not much differences in generated scratches and their formation mechanism. In this study, the scratches were investigated as a function of polishing conditions with possible explanation on formation mechanism in ILD CMP.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.5
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• pp.149-158
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• 2002

Recently, the minimum line width shows a tendency to decrease and the multi-level increases in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. However there are several defects in CMF, such as micro-scratches, abrasive contaminations and non-uniformity of polished wafer edges. Wet etching process including spin-etching can eliminate the defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(Interlayer-Dielectric) was removed by CMP and wet etching process using DHF(Diluted HF) in order to investigate the possibility of planrization by wet etching mechanism. In the thin film wafer, the results were evaluated from the viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And the pattern step heights were also compared for the purpose of planarity characterization of the patterned wafer. Moreover, Chemical polishing process which is the wet etching process with mechanical energy was introduced and evaluated for examining the characteristics of planarization.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.11a
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• pp.41-41
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• 1998

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.7
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• pp.311-315
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• 2002

Chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric (ILD) layers of multi-layer interconnections. In this paper, we studied the characteristics of polishing pad, which can apply shallow trench isolation (STI)-CMP process for global planarization of multi-level interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was detected less than 2 on JR111 pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and device yield.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1117-1120
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• 2001

Chemical mechanical planarization(CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There have been serious problems in CMP in terms of repeatability and defects in patterned wafers. Since IBM's official announcement on Copper Dual Damascene(Cu2D) technology, the semiconductor world has been engaged in a Cu2D race. Today, even after~3years of extensive R&D work, the End-of-Line(EOL) yields are still too low to allow the transition of technology to manufacturing. One of the reasons behind this is the myriad of defects associated with Cu technology. Especially, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasive and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using Ce$O_2$ is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method for developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.651-652
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• 2005

Chemical mechanical polishing (CMP) has emerged as the planarization technique of choice in integrated circuit manufacturing. Especially, polishing pad is considered as one of the most important consumables because of its properties. Generally, conventional polishing pad has irregular pores and asperities. If conditioning process is except from whole polishing process, smoothing of asperities and pore glazing occur on the surface of the pad, so repeatability of polishing performances cannot be expected. In this paper, CMP pad with microstructure was made using micro-molding technology and repeatability of ILD(interlayer dielectric) CMP performances and was evaluated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.89-92
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• 2004

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). we investigated the performance of $WO_3$ CMP used silica slurry, ceria slurry, tungsten slurry. In this paper, the effects of addition oxidizer on the $WO_3$ CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.188-191
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• 2003

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). we investigated the performance of $WO_3$ CMP used silica slurry, ceria slurry, tungsten slurry. In this paper, the effects of addition oxidizer on the $WO_3$ CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity.