• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.806-813
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• 2009

This paper presents a modem chip design for high-speed wireless communications. Among the high-speed communication technologies, we design the UWB (Ultra-Wideband) modem SoC (System-on-Chip) Chip based on a MB-OFDM scheme which uses wide frequency band and gives low frequency interference to other communication services. The baseband system of the modem SoC chip is designed according to the standard document published by WiMedia. The SoC chip consists of FFT/IFFT (Fast Fourier Transform/Inverse Fast Fourier Transform), transmitter, receiver, symbol synchronizer, frequency offset estimator, Viterbi decoder, and other receiving parts. The chip is designed using 90nm CMOS (Complementary Metal-Oxide-Semiconductor) procedure. The chip size is about 5mm x 5mm and was fab-out in July 20th, 2009.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.618-633
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• 2000

In this paper, a Gaussian interpolation filter and cubic interpolation filter are presented to do more accurate channel estimation compared to the conventional linear interpolation filter for COFDM systems. In addition to an interpolation filter, a low pass filter using FFT and IFFT is also presented to reduce the noisy components of a channel estimate obtained by an interpolation filter. Channel estimates after low-pass filtering combined with interpolation filters can lower the error floor compared to the use of only interpolation filters. Computer simulation demonstrates that the presented channel estimation methods exhibit an improved performance compared to the conventional linear interpolation filter for COFDM systems in time-varying multipath fading channel and0.1 ~ 0.2 dB of Eb/No difference at BER=10-4 when the perfect channel estimation is compared.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.6
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• pp.286-295
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• 2006

This paper presents a design of a real-time software GPS receiver which runs on a PC. The software GPS receiver has advantages over conventional hardware based receivers in terms of flexibility and efficiency in application oriented system design and modification. In odor to reduce the processing time of the software operations in the receiver, a shared memory structure is used with a dynamic data control, and the byte-type IF data is processed through an Open Multi-Processing technique in the mixer and integrator which requires the most computational load. A high speed data acquisition device is used to capture the incoming high-rate IF signals. The FFT-IFFT correlation technique is used for initial acquisition and FLL assisted PLL is used for carrier tracking. All software modules are operated in sequence and are synchronized with pre-defined time scheduling. The performance of the designed software GPS receiver is evaluated by running it in real-time using the real GPS signals.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1378-1386
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• 2004

In this paper, we propose an OFDM scheme to increase the BER performance. The proposed OFDM scheme makes the baseband OFDM signal by using the oversampled OFDM signal values which are obtained by inserting N(=2$\^$k/) zeros and carrying out 2N point IFFT. In the demodulation part, the sampling operation for A/D conversion is carried out with the 2 times high sampling speed. 2 N point FFT is carried out for the data demodulation. In this paper, we show, with the mathematical method and the computer simulation, that the SNR of the proposed OFDM scheme is 3 dB higher than that of the conventional OFDM in the same AWGN channel conditions given.

• The Journal of the Acoustical Society of Korea
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• v.29 no.1
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• pp.41-47
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• 2010

The pitch alteration technique for voice conversion is classified in time domain, frequency domain and hybrid domain. The Hybrid domain method has a merit of clearness and natural-ness of pitch altered speech but has the major drawback of long processing time. In this paper, we proposed a new method that can reduce the processing time of pitch alteration in time-frequency hybrid domain. We omitted the bit-reversing process of FFT and IFFT in changing the processing domain. Therefore we can reduce the processing time by 86.26% to the conventional method with same quality.

• Journal of Information Processing Systems
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• v.15 no.3
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• pp.670-681
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• 2019

Orthogonal frequency division multiplexing (OFDM) is a system which is used to encode data using multiple carriers instead of the traditional single carrier system. This method improves the spectral efficiency (optimum use of bandwidth). It also lessens the effect of fading and intersymbol interference (ISI). In 1995, digital audio broadcast (DAB) adopted OFDM as the first standard using OFDM. Later in 1997, it was adopted for digital video broadcast (DVB). Currently, it has been adopted for WiMAX and LTE standards. In this project, a Verilog design is employed to implement an OFDM transmitter (DAC block) and receiver (FFT and ADC block). Generally, OFDM uses FFT and IFFT for modulation and demodulation. In this paper, 16-point FFT decimation-in-frequency (DIF) with the radix-2 algorithm and direct summation method have been analyzed. ADC and DAC in OFDM are used for conversion of the signal from analog to digital or vice-versa has also been analyzed. All the designs are simulated using Verilog on ModelSim simulator. The result generated from the FFT block after Verilog simulation has also been verified with MATLAB.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.309-312
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• 2004

This paper proposes the architecture of UWB OFDM communication system. More high data rate is requested in the 128-point FFT/IFFT of the UWB OFDM communication system than the conventional communication systems. So, the proposed architecture uses pipeline and parallel architecture. For a highly efficient architecture, the optimal clipping power and the input quantization bits are found in simulation. The hardware complexity of the proposed architecture is presented is consideration of Adder, Register and Complex Multiplier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.233-239
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• 2001

Among the operations in frequency domain for ADSL G.LITE Modem to perform, FFT and FEQ are most computation-intensive part, of which many researches have been focused on the efficient implementation. Previous papers suggested hardwares suitable for ADSL G.DMT system, which is not feasible for simple G.LITE system. The analysis of frequency domain operations and computational efficiency according to the allocation of hardware resources is performed in this paper. The suggested processor has the structure of one real multiplier and two real adders connected in parallel, which can perform the operations efficiently through the pipeline- and/or parallel-type job scheduling. The suggested processor uses less hardware resources than Kiss\`s ALU structure or FFT/IFFT processor suggested by Wang, so the suggested one is more suitable for G.LITE system than previous works.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.15-16
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• 2006

In this paper, we propose an adaptive SLM scheme based on peak observation for PAPR reduction of OFDM signals. The proposed scheme is composed of three steps: peak scaling, sequence selection, and SLM procedures. In the first step, the peak signal samples in the IFFT outputs of the original input sequence are scaled down. In the second step, the sub-carrier positions where power difference between the original input sequence and the FFT outputs of the scaled signal is large, are identified. Then, the phase sequences which have the maximum number of phase-reversed sequence words only for these positions, are selected. Finally, only using the selected phase sequences, the generic SLM procedure is performed for the original input sequence. Simulation results reveal that the proposed adaptive SLM remarkably reduces the complexity in terms of IFFT and PAPR calculations than the conventional SLM, while maintaining the PAPR reduction performance.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.153-156
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• 2002

FFT/IFFT block is very important module to determine the performance of OFDM system. This block has been implemented using several FFT algorithms such as radix-2, radix-4 etc. However SRFFT algorithm has not been implemented because of the complexity for implementation. This paper proposes a serial-pipeline SRFfT for OFDM system. The serial-pipeline SRFFT is optimized to use a serial input and serial output. We have implemented the SRFFT block using anam 0.25 Um five-metal process. The simulation show that the SRFFT block can operate about 200MHz. This architecture could be adapted to IEEE 802.lla wireless LAN standard.