• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.368-376
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• 2006

This paper describes a Fcore_GenSim(Parameterized FFT Core Generation & Simulation Program), which can be used as an essential If(Intellectual Property) in various OFDM modem designs. The Fcore_Gensim is composed of two parts, a parameterized core generator(PFFT_CoreGen) that generates Verilog-HDL models of FFT cores, and a fixed-point FFT simulator(FXP_FFTSim) which can be used to estimate the SQNR performance of the generated cores. The parameters that can be specified for core generation are FFT length in the range of 64 ~2048-point and word-lengths of input/output/internal/twiddle data in the range of 8-b "24-b with 2-b step. Total 43,659 FFT cores can be generated by Fcore_Gensim. In addition, CBFP(Convergent Block Floating Point) scaling can be optionally specified. To achieve an optimized hardware and SQNR performance of the generated core, a hybrid structure of R2SDF and R2SDC stages and a hybrid algorithm of radix-2, radix-2/4, radix-2/4/8 are adopted according to FFT length and CBFP scaling.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.42-47
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• 2020

In OFDM-based very high-speed communication systems, FFT/IFFT processor should have several properties of low-area and low-power consumption as well as high throughput and low processing latency. Thus, radix-2k MDF (multipath delay feedback) architectures by adopting pipeline and parallel processing are suitable. In MDF architecture, the feedback memory which increases in proportion to the input signal word-length has a large area and power consumption. This paper presents a feedback memory size reduction method of radix-22 MDF IFFT processor for OFDM applications. The proposed method focuses on reducing the feedback memory size in the first two stages of MDF architectures since the first two stages occupy about 75% of the total feedback memory. In OFDM transmissions, IFFT input signals are composed of modulated data and pilot, null signals. In order to reduce the IFFT input word-length, the integer mapping which generates mapped data composed of two signed integer corresponding to modulated data and pilot/null signals is proposed. By simulation, it is shown that the proposed method has achieved a feedback memory reduction up to 39% compared to conventional approach.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.86-92
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• 2008

Othogonal Frequency Division Multiplexing(OFDM) has been taken notice of 4th generation communication method because it has a merit of high data rate(HDR). To realize HDR communication, The OFDM a s high efficient Fast-Fourier-Transform (FFT)/Inversion FFT (IFFT) processor. Currently OFDM is realized by Digital Signal Processor(DSP) but it consumes a lot of Power. Therefore, current-mode FFT LSI has been proposed for compensation of this demerit. In this paper, we propose IVC for current-mode FFT LSI. From the simulation result, the output value of IVC is more than 3V when the value of FFT Block output is more than $7.35{\mu}A$. The output value of IVC is lower than 0.5V when the value of FFT Block output is lower than $0.97{\mu}A$. Designed IVC Low-power Current mode FFT LSI will contribute to the operation of current-mode FFT LSI and the development of next generation wireless communication systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.2
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• pp.97-102
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• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.

• Speech Sciences
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• v.10 no.2
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• pp.57-64
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• 2003

The cepstrum coefficients are the most popular feature for speech recognition or speaker recognition. The cepstrum coefficients are also used for speech synthesis and speech coding but has major drawback of long processing time. In this paper, we proposed a new method that can reduce the processing time of FFT cepstrum analysis. We use the normal ordered inputs for FFT function and the bit-reversed inputs for IFFT function. Therefore we can omit the bit-reversing process and reduce the processing time of FFT ceptrum analysis.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.11-20
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• 2016

In this paper, we propose the channel estimation scheme for Long Term Evolution-Advanced (LTE-A) downlink system. The proposed scheme uses the fast fourier transform (FFT) interpolation scheme for the user moving at a high speed. The FFT interpolation scheme converts the channel frequency response obtained from least square (LS) or minimum mean square error (MMSE) channel estimation scheme to time domain channel impulse response by taking the inverse FFT (IFFT). After windowing the channel response in the time domain, we can obtain the channel frequency response by taking the FFT. We perform the system level simulation based on 20MHz bandwidth of 3GPP LTE-A downlink system. Simulation results show that the proposed channel estimation scheme can improve signal-to-noise-plus-interference ratio (SINR), throughput, and spectral efficiency of conventional system.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1488-1491
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• 1987

This paper describes 16-point FFT processor using systolic array and its implementation into VLSI. Designed FFT processor executes FFT/IFFT arithmetic under mode control and consists of cell array, array controller and input/output buffer memory. For design for testibility, we added built-in self test circuit into designed FFT processor. To verify designed 16-point FFT processor, logic simulation was performed by YSLOG on MICRO-VAXII. From the simulation results, it is estimated that the proposed FFT processor can perform 16-point FFT in about 4400[ns].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.1030-1038
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• 2013

The proposed Alamouti coded OFDM effectively cancels Inter Carrier Interference (ICI) due to frequency offset between distributed antennas. The conventional Alamouti coded OFDM schemes to mitigate ICI utilize N-point Inverse Fast Fourier Transform/Fast Fourier Transform (IFFT/FFT) operations for OFDM modulation and demodulation processes with total N subcarriers. However, the performance degrades because ICI is also repeated in N periods due to the property of N-point IFFT/FFT operation. In order to avoid this problem, null data are used at the subcarriers with large ICI and thus, data rate decreases. The proposed scheme employs 2N-point IFFT/FFT instead of N-point IFFT/FFT in order to increase sampling rate. By increasing sampling rate, the amount of interference significantly decreases because the period of ICI also increases. The proposed scheme increases the data rate and improves the performance by reducing amount of ICI and the number of null-data. Furthermore, the gain of the performance and data rate of the proposed scheme is significant with higher modulation such as 16-Quadarature Amplitude Modulation (QAM) or 64-QAM.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.263-266
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• 2002

An optical method for surface roughness estimation based on statistical analysis of the light intensity of a scattered laser beam pattern. The method is very simple but has a disadvantage that no more information than the averaged roughness is estimated. In this study a new try was conducted to derive more advanced surface information from the details of the light intensity distribution. Some periodic ripples among the light intensity distribution being assumed to relate with scratch left on the machined surface, a corresponding surface profile is estimated from the ripples using FFT and IFFT algorithm. IFFT technique is used to extract some dominant signal components among the intensity distribution. Compared to the measured profiles by a stylus type surf-tester, the profiles obtained through the proposed method are probably acceptable in a sense of the profile shape. Calibration of the amplitude needs more works in the future.