• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.9
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• pp.461-466
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• 1999

The switched reluctance motor (SRM) would have torque ripple if not operated with an MMF waveform specified for switching angle and phase voltage. This paper describes the robustic control scheme that permits the phase torque to be flat by PLL(Phase Locked Loop) controller. In this control scheme, the locked phase signal of PLL controls the switching dwell angle and it's loop filter signal controls the switching voltage adaptively. Experimental results show that stable dynamic performance is obtained for torque and speed together with low torque ripple on the operation of variable loads.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.1188-1191
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• 2003

In this paper, we focus our attention on the improvement of locking time and jitter parameter and propose the new structure of PLL which combined with the FVC, FOVI Matcher(FVC-Output and VCO-input Matching Circuit), Control Circuit and the conventional charge pump PLL. Using fast operation characteristics of the FVC, the circuit matching FVC-Output and VCO-input (FOVI Matcher) made to synchronize very fast. Fast locking time is usually required for application where the PLL has to settle rapidly if they switch from an idle mode to a normal mode and to track high-frequency data bit rate in data recovery systems. After a fast acqusition is achieved by the using the FVC, the conventional PLL operates for removing the phase error between the reference signal and the feedback signal. Therefore this structure can improve the trade-off between acquisition behavior and locked behavior.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.3
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• pp.19-25
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• 2000

In this paper, we describe RF receiver module for IMT-2000 handset with 5 MHz channel bandwidth. The fabricated RF receiver module consists of Low Noise Amplifier, RF SAW filter, Down-converter, If SAW filter, AGC and PLL Synthesizer. The NF and IIP3 of LNA is 0.8 dB, 3 dBm at 2.14 GHz, conversion gain of down-converter is 10 dB, dynamic range of AGC is 80 dB, and phase noise of PLL is -100 dBc at 100 kHz. The receiver sensitivity is -110 dBm, adjacent channel selectivity is 48 dBm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.851-856
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• 2006

This paper studies about design of a transceiver using a single PLL. The transceiver has bandwidth of $424.7\sim424.95MHz$ and the communication method used 21 channels 12.5 KHz channel bandwidth and FSK modulation/demodulation method. Also, we designed low power wireless transceiver for data transmission using a single PLL. Finally, the transceiver set achieves the following characteristics : 8.15dBm output power, 45.97dBc spurious property.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.485-487
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• 2006

This paper describes a frequency synthesizer designed in a $0.25{\mu}m$ CMOS technology for using local oscillators for the IF stages. The design is focused mainly on low-power characteristics. A simple ring-oscillator based VCO is used, where a single control signal can be used for variable resistors. The designed PLL includes all building blocks for elimination of external components, other than the crystal, and its operating frequency can be programmed by external data. It operates in the frequency range of 250MHz to 800MHz and consumes l.08mA at 500MHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset. The die area is $1.09mm^2$

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.108.2-108
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• 2001

This paper presents the application of adaptive phase-locked loop (adaptive PLL) technique to control the process variable of the process control system. The adaptive algorithm is related to the error. When the error of the system is changed, the adaptive gain will be directly changed according to the error. If the value of the adaptive gain is large, the value of the error will be large. In this experiment, the reference input is 50% step input. The experimental result in controlling the first order lag process by the adaptive PLL shows that the response of the controlled system has no overshoot, short rise time, and zero steady-state error. The experimental result also shows that when the output disturbance enters to the process control system, the adaptive PLL can maintain the stability of the system and the effect of the output disturbance can also be fast rejected. The adaptive PLL has better performance ...

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.155-158
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• 1999

This paper describe the design and measurements of dual PLL for IMT-2000 cellular phone. As a result, dual PLL was well-operated in the RF frequency ranges of 2300 ~ 2360 MHz and If frequency of 380 MHz. The output power of -4.28 ㏈m, phase noise of -107.66㏈c/Hz at 100KHz frequency offset, lock time of 675.6$mutextrm{s}$ were obtained at 2330MHz. The output power of -4.78 ㏈m, phase noise of -115.28㏈c/Hz were also obtained at 380MHz.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.11-20
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• 2005

In this paper, we deal with the research about a S/PDIF (Sony Philips Digital Interface) receiver which can operate without PLL (Phase Locked Loop) circuits. Although a S/PDIF receiver is used in most audio devices and audio processors in these days. yet there are only few domestic researches about S/PDIF. Currently used commercial DACs (Digital-to-Analog Converters) which can decode S/PDIF signals, have a PLL circuit inside them. The PLL makes it possible to extract clock information from S/PDIF digital signal and to synchronize a clock signal with input signals. But the PLL circuit makes many diffculties in designing the SOC (System On Chips) of VLSIs (Vew Large Scale Integrated Ciruits) because it is an "analog circuit". We proposed a S/PDIF receiver which doesn't have PLL circuits and only has Pure digital circuits. The key idea of the proposed S/PDIF receiver. is to use the ratio between a 16 MHz basic input clock and S/PDIF signals. After having decoded hundreds thousands S/PDIF inputs, it went to prove that a S/PDIF receiver can be designed with pure digital circuits and without any analog circuits such as PLL circuits. We have confidence that the proposed S/PDIF receiver can be used as an IP (Intellectual Property) for the SOC design of the digital circuits.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.817-820
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• 1999

In this paper, we describes RF receiver module for IMT-2000 handset with 5MHz channel bandwidth. The fabricated RF receiver module consists of Low Noise Amplifier-, RF SAW filter, Down-converter, IF SAW filter, AGC and PLL Synthesizer. The NF and IIP3 of LNA is 0.8㏈, 3㏈m at 2.14㎓, conversion gain of downconverter is l0㏈, dynamic range of AGC is 80㏈, and phase noise of PLL is -100 ㏈m, at 100KHz. The receiver sensitivity is -110㏈m, adjacent channel selectivity is -48㏈m.