• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.9A
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• pp.803-813
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• 2005

This paper explores the throughput performance of CSMA/CA-based DCF protocol over frequency-selective, slow Ricean fading channels with both the $E_{b}/N_{o}$ and BER at the MAC layer in the 802.1 la wireless LAN. By exploring the throughput of DCF protocol with the data rate of 6Mbps, 12 Mbps, 24 Mbps and 54 Mbps, we find the fact that the higher the $E_{b}/N_{o}$ be and the less the BER be, the higher the throughput be.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.431-434
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• 2004

In this paper we present about implementation of channel coder and Viterbi decoder for Mobile communication & IEEE 802.11a Wireless LAN. In the IEEE 802.11a Wireless LAN decoding provided that Viterbi algorithm and convolutional encoder by constraint k=7, ($133_8,\;171_8$) for channel error correction. This Paper presents a novel survivor memory management and decoding techniques with sequential backward state transition control in the trace-back Viterbi decoder, In order to verification we provide to the examples of circuit design and decoding results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7A
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• pp.794-806
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• 2004

This paper deals with correction of frequency offset and analysis of quantization angle noise in the IEEE 802.1la OFDM system. The rotation phase per symbol due to the carrier frequency offset is estimated from auto-correlation of the short Preambles, which are over-sampled for the reduction of noise in OFDM signals. The pilot signals are introduced to estimate the rotation phase per OFDM symbol due to estimation error of the carrier frequency offset and the sampling frequency onset. During the estimation and correction of the frequency onsets, a CORDIC processor and a look-up table are used for the conversion between a rotation phase and its complex number. Being calculated by a limited number of bits in the CORDIC processor and the look-up table, the rotation phase and its complex number have quantization angle errors. The quantization errors are analyzed as SNR (signal to noise ratio) due to the quantization bit numbers. The minimum bit number is suggested to meet the specification of IEEE 802.1la properly. Finally, the quantization errors are evaluated through simulations on number of quantization bits and SNR of received signals.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.461-464
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• 2002

OFDM is a promising technology for high speed multimedia communication. In this paper, Software IPs for IEEE 802.11a OFDM system are designed and optimized for TI's TMS320C6201 fixed-point DSP. Then considering the execution cycles of the target DSP for each functions of the system, an efficient HW/SW partitioning method is proposed and according to this results, high speed Viterbi decoder hardware IP for 802.11a system is designed and verified.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.7
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• pp.741-753
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• 2008

This paper explores the throughput performance of CSMA/CA-based DCF protocol over both ideal channels and fading channels with payload size at the MAC layer in the 802.11a wireless LAN. In the ideal channel, there are no errors and at the transmission cycle there is one and only one active station which always has a packet to send and other stations can only accept packets and provide acknowledgements. In the fading channel, bit errors appear in the channel randomly and the number of stations is assumed to be fixed. And each station always has packets for transmission. In other words, we operate in saturation conditions. Up to now conventional research work about DCF throughput analysis of IEEE 802.11 a wireless LAN has been done over the ideal channel, but this paper is done over the Rayleigh/Ricean fading channel. So, the ratio of received average energy per bit-to-noise power spectral density $E_b/N_o$ is set to 25 dB and the ratio of direct-to-diffuse signal power in each sub-channel $\xi$ is set to 6 for combined Rayleigh/Ricean fading channel. In conclusion, it is shown that the saturation throughput is always less than the maximum throughput at all the payload size and the higher the transmission rate be, the higher the decreasing rate of saturation throughput compared to the maximum throughput be.

• Proceedings of the KAIS Fall Conference
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• 2004.11a
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• pp.179-181
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• 2004

This study presents a cylindrical WLAN antenna for MIMO systems. Three typical inverted-F antennas, which have individual ground plane, are placed on the cylindrical rod. An optimum antenna is fabricated by theoretical prediction and numerical simulation. The proposed antenna here can operate in the 5GHz bands(IEEE 802.1la) and be adopted in small wireless communication systems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1152-1160
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• 2004

OFDM technique was adopted as the standard of IEEE 802.1 la and it has been widely used for wireless LAN, European DVB/DAB system, Korean DMB system. In the standard of IEEE 802.11a the data packet is composed of two parts, preamble and data. Preamble is composed of short pilots and long pilots, which are used for synchronization and estimation of frequency offset and channel. We can also compensate phase noise effect in the transceiver by using above pilots. The phase noise is more complicate than frequency offset and seriously affects system performance. In this paper, we newly propose CPE and ICI simultaneous compensation method to compensate phase noise generated by transceiver oscillator and compare with previous studies. As results, phase noise effect can be significantly compensated by CPE cancellation method, PNS algorithm and our proposed CPE and ICI compensation method. Especially, the proposed CPE and ICI compensation method can achieve the best BER performance compared with original OFDM, CPE cancellation method and PNS algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1106-1113
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• 2005

This paper presents a dual-band mixer for multi-standards of IEEE 802.1la/b/g using a single local oscillator, so as to improve the defects of legacy systems. Those systems have duplicate local oscillators and mixers to handle dual band signals, increasing complexity of system and power loss. The proposed circuit shows 11.6 dB, 16.8 dB of conversion loss and 8.77 dBm, 12.5 dBm of IIP3(Input 3rd Intercept Point) for respective bands when the two RF inputs of 2.452 and 5.260 GHz are down-converted to the identical 356 MHz If frequency. The RF-LO isolations are measured 36 dB, 41 dB at each frequencies and over 50 dB of LO-IF isolations are achieved at all cases.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.2
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• pp.268-277
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• 2001

In this paper, the system performance with the convolution code using a Viterbi decoding and the one tap LMS equalizer applied to the OFDM system, which is suitable for IEEE 802.1la wireless LAN in indoor wireless channel, is analyzed through computer simulation. Indoor wireless channel is modeled as Rician fading channel, and QPSK and 16QAM scheme are used for subchannel modulation. In Rician fading channel with the power ratio of the direct path signal to the scattered signals, K=5 dB, BER of $10^{-4}$ is satisfied if the SNRs of the QPSK/OFDM and the 16QAM/OFDM are 8.6 dB and 19.2 dB in hard decision and 5.3 dB and 9.8 dB in soft decision, respectively. Compared with convolution code scheme, it is observed that 16QAM/OFDM system with the one tap LMS equalizer has the performance improvement of 8.6 dB and 2 dB in hard decision and soft decision, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.