• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.956-958
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• 2012

In this paper proposes improve the quality of the GIS software, GIS software quality metrics that can be measured based on ISO/IEC 9126.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.958-964
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• 2010

Histogram Equalization(HE) is one of the well known methods for contrast enhancement. but, it did not applied directly due to side effects such as significant change in brightness or washed out appearance. Many conventional method try to overcome this problem but they did not guarantee various image or depend on user define parameter. In this paper, an Adaptive histogram Compensated Histogram Equalization(ACHE) is proposed for contrast enhancement. ACHE has a parameter that based on median of input image. Histogram of input image is compensated according to parameter. And then finally compensated histogram is equalized. Experimental results show that proposed method suppresses side effects such as detail loss or washed out appearance. Moreover, parameter calculated automatically with low computation complexity. As a result, it could applies FPD directly.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.3
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• pp.22-29
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• 2015

The AC-LED driving system which is connected directly to alternative current source is suitable for commercialization because of it's simple structure and low cost. However, it requires additional circuits compensating for current differences between the parallel connected LED strings. In this paper, we proposed the circuit compensating for current error of the three LED strings using the Y type balancing transformer. The proposed Half-bridge AC Chopper LED driving system used the ferrite material's balancing transformer. at the same time, it is able to dimming control. The proposed system is applied to 80W AC-LED module consist of three parallel strings. Experiment results present that Power factor and THD measured with power analyzer are 0.958 and 26.473% respectively satisfied with IEC61000-3-2 harmonics standard.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.11-20
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• 2005

In this paper, we deal with the research about a S/PDIF (Sony Philips Digital Interface) receiver which can operate without PLL (Phase Locked Loop) circuits. Although a S/PDIF receiver is used in most audio devices and audio processors in these days. yet there are only few domestic researches about S/PDIF. Currently used commercial DACs (Digital-to-Analog Converters) which can decode S/PDIF signals, have a PLL circuit inside them. The PLL makes it possible to extract clock information from S/PDIF digital signal and to synchronize a clock signal with input signals. But the PLL circuit makes many diffculties in designing the SOC (System On Chips) of VLSIs (Vew Large Scale Integrated Ciruits) because it is an "analog circuit". We proposed a S/PDIF receiver which doesn't have PLL circuits and only has Pure digital circuits. The key idea of the proposed S/PDIF receiver. is to use the ratio between a 16 MHz basic input clock and S/PDIF signals. After having decoded hundreds thousands S/PDIF inputs, it went to prove that a S/PDIF receiver can be designed with pure digital circuits and without any analog circuits such as PLL circuits. We have confidence that the proposed S/PDIF receiver can be used as an IP (Intellectual Property) for the SOC design of the digital circuits.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.91-97
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• 1995

This paper describes the implementation of a multi-channel audio codec for HETV. This codec has the features of the 3/2-stereo plus low frequency enhancement, downward compatibility with the smaller number of channels, backward compatibility with the existing 2/0-stereo system(MPEG-1 audio), and multilingual capability. The encoder of this codec consists of 6-channel analog audio input part with the sampling rate of 48 kHz, 4-channel digital audio input part and three TMS320C40 /DSPs. The encoder implements multi-channel audio compression using a human perceptual psychoacoustic model, and has the bit rate reduction to 384 kbit/s without impairment of subjective quality. The decoder consists of 6-channel analog audio output part, 4-channel digital audio output part, and two TMS320C40 DSPs for a decoding procedure. The decoder analyzes the bit stream received with bit rate of 384 kbit/s from the encoder and reproduces the multi-channel audio signals for analog and digital outputs. The multi-processing of this audio codec using multiple DSPs is ensured by high speed transfer of date between DSPs through coordinating communication port activities with DMA coprocessors. Finally, some technical considerations are suggested to realize the problem of real-time operation, which are found out through the implementation of this codec using the MPEG-2 layer II sudio coding algorithm and the use of the hardware architecture with commercial multiple DSPs.