• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.324-336
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• 2000

The paper proposes an efficient buffer management scheme to enhance performance of the disk I/O system. Without any user level information, the proposed scheme automatically detects the block reference patterns of applications by associating block attributes with forward distance of a block. Based on the detected patterns, the scheme applies an appropriate replacement policy to each application. We also present a new block allocation scheme to improve the performance of buffer cache when kernel needs to allocate a cache block due to a cache miss. The allocation scheme analyzes the cache hit ratio of each application based on block reference patterns and allocates a cache block to maximize cache hit ratios of system. These all procedures are performed on-line, as well as automatically at system level. We evaluate the scheme by trace-driven simulation. Experimental results show that our scheme leads to significant improvements in hit ratios of cache blocks compared to the traditional schemes and requires low overhead.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.5
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• pp.34-42
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• 2002

In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.4
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• pp.372-381
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• 2001

In this paper SEED, the Korea Standard 128-bit block cipher algorithm is implemented with VHDL and mapped into one FPGA. SEED consists of round key generation block, F function block, G function block, round processing block, control block and I/O block. The designed SEED is realized in an FPGA but we design it technology-independently so that ASIC or core-based implementation is possible. SEED requires many hardware resources which may be impossible to realize in one FPGA. So it is necessary to minimize hardware resources. In this paper only one G function is implemented and is used for both the F function block and the round key block. That is, by using one G function sequentially, we can realize all the SEED components in one FPGA. The used cell rate after synthesis is 80% in Altem FLEXI0KlOO. The resulted design has 28Mhz clock speed and 14.9Mbps performance. The SEED hardware is technology-independent and no other external component is needed. Thus, it can be applied to other SEED implementations and cipher systems which use SEED.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.1
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• pp.23-29
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• 2005

This paper presents the characteristics of leakage currents flowing through ZinC Oxide(ZnO) surge arrester blocks under mixed direct and 60 Hz alternating voltages. A mixed voltage, in which an alternating voltage is superimposed upon a direct voltage, appears on the HVDC system network. The mixed direct and alternating voltage generator with a peak open-circuit of 10 kV was designed and fabricated. The leakage currents and V-I curves for the fine and used ZnO surge arrester blocks were measured as a function of the voltage ratio k, where the voltage ratio k is defined as the ratio of the peak of alternating voltage to the peak of the mixed voltages. The resistive component in the leakage current in the low conduction region is significantly increased with increasing the voltage ratio k. The V-I characteristic curves for the mixed voltages lies between the direct and alternating characteristics, and the cross-over phenomenon in the high conduction region was appeared.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.91-91
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• 2012

We aim in synthesizing various functional thin films thinner than ~ 10 nm for environmental applications and photovoltaic devices. Atomic layer deposition is used for synthesizing inorganic thin films with a precise control of the film thickness. Several examples about application of our thin films for removing volatile organic compounds (VOC) will be highlighted, which are summarized in the below. 1) $TiO_2$ thin films prepared by ALD at low temperature ($<100^{\circ}C$) show high adsorption capacity for toluene. In combination with nanostructured templates, $TiO_2$ thin films can be used as building-block of high-performing VOC filter. 2) $TiO_2$ thin films on carbon fibers and nanodiamonds annealed at high temperatures are active for photocatalytic oxidation of VOCs, i.e. photocatalytic filter can be created by atomic layer deposition. 3) NiO can catalyze oxidation of toluene to $CO_2$ and $H_2O$ at $<300^{\circ}C$. $TiO_2$ thin films on NiO can reduce poisoning of NiO surfaces by reaction intermediates below $200^{\circ}C$. We also fabricated inverted organic solar cell based on ZnO electron collecting layers on ITO. $TiO_2$ thin films with a mean diameter less than 3 nm on ZnO can enhance photovoltaic performance by reducing electron-hole recombination on ZnO surfaces.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.10
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• pp.413-420
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• 2013

Redundant arrays of independent disks (RAID) without a power-fail-safe component in small and mid-sized business suffers from intolerably long resynchronization time after a unclean power-failure. Data blocks and a parity block in a stripe must be updated in a consistent manner, however a data block may be updated but the corresponding parity block may not be updated when a power goes off. Such a partially modified stripe must be updated with a correct parity block. However, it is difficult to find which stripe is partially updated (inconsistent). The widely-used traditional parity resynchronization manner is a intolerably long process that scans the entire volume to find and fix inconsistent stripes. This paper presents a fast resynchronization scheme with a negligible overhead for small and mid-sized RAIDs. The proposed scheme is integrated into a software RAID driver in a Linux system. According to the performance evaluation, the proposed scheme shortens the resynchronization process from 200 minutes to 5 seconds with 2% overhead for normal I/Os.

• Journal of the Korean Society of Clothing and Textiles
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• v.33 no.2
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• pp.187-199
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• 2009

Recently, the quality and design of the children's wear is being improved remarkably. Following the trend, the need for the research on the pattern making of children's wear is growing. At first, we tried to find out how the industry is doing the pattern making job through interview. Results are as follows. The target age ranges from 5 to 11 years old. For the sample size of pattern making, 7 years of age is preferred. It is not usual to develop the design pattern from the bodice block pattern. Instead, they use middle block pattern for each item, such as blouse, shirt, pants, skirt or jacket. Starting from these middle block pattern, they prepare individual designs. With the results, the aim of the research became to develop one of most frequently used middle block pattern. The blouse block pattern was selected for that purpose. To look into the existing patterns, we selected 4 methods, i.e. NM-method, T-method, O-method, E-methods. Theses patterns were compared through wearing test for the evaluation of comfort and fit using trial garments. The results indicated the NM-method was best among them. Specially waist line position, shoulder shape and size allowance was adequate. Alteration and adjustment of pattern draft was made onto the NM-method. Allowances for the bust circumference, across chest, across back and depth of arm was adjusted for better comfort as well as fine fit. Sidelines of the bodice and the underarm seam of the sleeves were curved for styling. After another wearing test, the final pattern was suggested as a blouse block pattern for 7 years old girl.

• The KIPS Transactions:PartD
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• v.18D no.3
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• pp.157-168
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• 2011

Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

• Aerospace Engineering and Technology
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• v.6 no.2
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• pp.171-179
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• 2007

The Test Equipment for the upper stage of KSLV-I has following functions via umbilical cable interface; external power supply, command output such as discrete and analog, data acquisition, CS-I interface simulation for first stage of KSLV-I and RS-422 serial communication for PDU. The main purpose of UTE is the experiment or function verification of system-level upper stage. To realize this system, we used PXI control system. The UTE is consisted of the PXI control system, power supply, terminal block, internal harness, connector panel and so on. The software functions of UTE are classified by four blocks. These are Discrete/Analog I/O control, PDU RS-422 serial communication control, power supply GPIB control and UTE remote control. In this paper, we will describe the design on the hardware and software of UTE.

• The Korean Journal of Pain
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• v.1 no.1
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• pp.106-119
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• 1988

For the relief of pain in 3 cases of whiplash syndromes (case I, II and IV) and in one of reflex sympathetic dystrophy (case III), we have carried out six intentional. total spinal blocks (TSB) which attempted two times in case I, three in case II and one in carte III whoso various symptoms were chronically unresponsive to the usual conservative treatments, and a time of cervical epidural and right suprascapular nerve block in case W whose acute symptom lasted 4 drys following the cervical injury (see fables from 1 to 9). During the 753, we have observed clinically the sequential charges of respiration, lid and pupil reflexes, body motion and consciousness. And checked the blood pressure, pulse rate and arterial Pco2. The effectiveness of those blocks has been assessed by using the Visual Analog Scale which is designed to measure the patient$\acute{s}$ subjective intensity of pain and also we have found out the sequelae following those blocks. The methods of the blocks were as the following: 1. Under the N.P.O. for 8~10 hours, the preparations of immediate cardiopulmonary resuscitation and premedication with atropine 0.5mg at thirty minutes before the TSB, it was performed by injecting the mixture of 2% mepivacaine 10 or 15ml and normal saline 10 or 5ml through No. 23 G. spinal needle into the subarachnoid space of $C_7-T_1$ interspinous region with fully flexed neck on the lateral posture. Immediately after the injection of the local anesthetic in the lateral position, the patient$\acute{s}$ were hasten to change Trendelenburg$\acute{s}$ position in order to act the drugs cephalad and to make easy controlled respiration with oxygen. 2. The cervical epidural block was done by injecting the mixture of 0.5% bupivacaine 4ml, normal saline 4ml and triamcinolone 15mg through No. 18 G. Tuohy needle into the epidural space on the same region and posture as the above without premedication.7he suprascapular nerve block was done by injecting of 0.5% bupivacaine 3ml only into the right suprascapular fossa on the sitting posture. The results were as the following: 1. The cessation of respiration was seen within 5 minutes following the subarachnoidal injection of the above 20ml mixture in 2 to 3 minutes and then soon the consciousness began to disappear. The loss of Lid and pupil reflexes noted between 5 to 10 minutes and the size of the dilated pupils was equal between 5 to 20 minutes, but the pupil of the dependent side on tile lateral position was dilated 1 to 3 minutes earlier than that of the independent. The patients had r=ever responded to any stimulations during the TSB except their heart funtion. 2. The recovery of the TSB was as the following, firstly the ankle and lower limb of the independent side began to move slightly with in 34 to 75 minutes after the injection and then that of the dependent Secondly the neck and upper limb moved 6 to 15 minutes later than the lower limb. Thirdly the self respiration began to appear between 40 to 80 minutes from the block. The lid and pupil reacted to touch and light respectively between 40 to 80 minutes but the pupil of the independent side responded earlier than that of the depends. Lastly the consciousness recovered completely between 80 to 125 minutes from the block. 3. In the cardiopulmonary function during the TSB, the blood pressure were stable except the 210/130 tory at the and block of case I. There were bradycardias between 65 to 85 minutes in case I and II but no arrythmia on the EKG. The level of the arterial Pco2 was maintained to 43~45 torr during the TSB. 4. The effectiveness of the above blocks was no pain(0%) in case IV, and light (10~20%) in case I and II but no improvement in case III. 5. The right arm weakness has been complicated as to be Injected accidently the "COLD" local anesthetic at the End block of case I.