• KIPS Transactions on Software and Data Engineering
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• v.4 no.9
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• pp.371-376
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• 2015

The Internet of Things (IoT) significantly increases the amount of data. Database compression is important for big data because it can reduce costs for storage systems and save I/O bandwidth. However, it could show low performance for write-intensive workloads such as OLTP due to the updates of compressed pages. In this paper, we present practical guidelines for the performance improvement of database compression. Especially, we propose the SELECTIVE strategy, which compresses only tables whose space savings are close to the expected space savings calculated by the compressed page size. Experimental results using the TPC-C benchmark and MySQL show that the strategy can achieve 1.1 times better performance than the uncompressed counterpart with 17.3% space savings.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.22-32
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• 1997

This paper proposes an imprecise compuitation model for DCT considering QOS of images and a two dimensional DCT architecture for imprecise computations. In case that many processes are scheduling in a hard real time system, the system resources are shared among them. Thus all processes can not be allocated enough system resources (such as processing power and communication bandwidth). The imprecise computtion model can be used to provide scheduling flexibility and various QOS(quality of service)levels, to enhance fault tolerance, and to ensure service continuity in rela time systems. The DCT(discrete cosine transform) is known as one of popular image data compression techniques and adopted in JPEG and MPEG algorithms since the DCT can remove the spatial redundancy of 2-D image data efficiently. Even though many commercial data compression VLSI chips include the DCST hardware, the DCT computation is still a very time-consuming process and a lot of hardware resources are required for the DCT implementation. In this paper the DCT procedure is re-analyzed to fit to imprecise computation model. The test image is simulated on teh base of this model, and the computation time and the quality of restored image are studied. The row-column algorithm is used ot fit the proposed imprecise computation DCT which supports pipeline operatiions by pixel unit, various QOS levels and low speed stroage devices. The architecture has reduced I/O bandwidth which could make its implementation feasible in VLSI. The architecture is proved using a VHDL simulator in architecture level.

• Journal of Digital Convergence
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• v.12 no.1
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• pp.379-388
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• 2014

We noted that substituting hard disk with high-performance storage device on SAN did not immediately result in getting high performance. Investigating the reason behind this leaded us to propose optimization schemes for high-performance storage system. We first got rid of the latency in the I/O process which is unsuitable for the high-performance storage device, added parallelism on the storage server, and applied temporal merge to Superhigh speed network protocol for improving the performance with small random I/O. The proposed scheme was implemented on the SAN with high-performance storage device and we verified that there were about 30% reduction on the I/O delay latency and 200% improvement on the storage bandwidth.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.7
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• pp.657-668
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• 2008

Traditional off-the-shelf file server has several potential drawbacks to store data blocks. A first drawback is a lack of practical de-duplication consideration for storing data blocks, which leads to worse storage capacity waste. Second drawback is the requirement for high performance computer system for processing large data blocks. To address these problems, this paper proposes a clustering backup system that exploits file fingerprinting mechanism for block-level de-duplication. Our approach differs from the traditional file server systems in two ways. First, we avoid the data redundancy by multi-level file fingerprints technology which enables us to use storage capacity efficiently. Second, we applied a cluster technology to I/O subsystem, which effectively reduces data I/O time and network bandwidth usage. Experimental results show that the requirement for storage capacity and the I/O performance is noticeably improved.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.7
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• pp.308-314
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• 2005

The 2 GHz film bulk acoustic wave resonator(FBAR), one of the most necessary device of the next generation mobile communication system, consisted of solidly mounted resonator(SMR) structure using Brags reflector, was researched in this paper The FBAR applied SiO$_{2}$ and W had large difference of the acoustic impedance to reflector Al to electrode and ZnO to piezoelectric layer. Specially, the FBAR applied the two-step deposition method to improve the c-axis orientation and increase reproducibility of the fabrication device had good performance. The electrical properties of plasma such as impedance, resistance, reactance, $V_{pp},\;I{pp}$, VSWR and phase difference of voltage and current, was analyzed and measured by RF sensor with the variable experiment process factors such as gas ratio, RF power and base vacuum level about concerning the thickness, c-axis orientation, adhesion and roughness. The FBAR device about the optimum condition resulted reflection loss(S$_{11}$) of -17 dB, resonance frequency of 1.93 GHz, electric-mechanical coefficient(k$_{eff}$) of 2.38 $\%$ and Qualify factor of 580. It was seen better qualify than the common dielectric filter at present and expected on business to the filter device of 2 GHz bandwidth with the MMIC technology.

• Progress in Superconductivity
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• v.2 no.1
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• pp.51-55
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• 2000

A $Y_1Ba_2Cu_3O_{7-\delta}$ square spiral microstrip antenna (YBCO antenna) was epitaxially grown on a $LaAlO_3$ substrate by laser ablation. Also fabricated was a gold square spiral microstrip antenna (gold antenna) having the same structure as that of the YBCO antenna in order to compare the properties of both antennas. Both the YBCO antenna and the gold antenna were operated in Ku (12-18 GHz) band, and their properties such as the return loss, SWR, power gain, and radiation patterns were investigated at 77 K. The return loss below -10 dB was obtained in two frequency ranges, i.e., 14.05-14.90 GHz, and 16-18 GHz for the YBCO antenna at 77 K (YBCO superconducting antenna), and in the frequency range of 15.05-17.60 GHz for the gold antenna at 77 K. The SWR bandwidths are 0.85 GHz and 2 GHz for the YBCO superconducting antenna, and 2.55 GHz for the gold antenna at 77 K. The gain improvement of the superconducting YBCO antenna over the gold antenna at 77 K was about 10 dB in the frequency range of 16 GHz to 18 GHz. The radiation patterns show the YBCO superconducting antenna has the omni-directional property of a spiral antenna.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1730-1736
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• 2015

This paper presents a 16-channel transimpedance amplifier (TIA) array implemented in a standard $0.18-{\mu}m$ CMOS technology for the applications of panoramic scan LADAR (PSL) systems. Since this array is the front-end circuits of the PSL systems to recover three dimensional image for unmanned vehicles, low-noise and high-gain characteristics are necessary. Thus, we propose a voltage-mode inverter TIA (I-TIA) array in this paper, of which measured results demonstrate that each channel of the array achieves $82-dB{\Omega}$ transimpedance gain, 565-MHz bandwidth for 0.5-pF photodiode capacitance, 6.7-pA/sqrt(Hz) noise current spectral density, and 33.8-mW power dissipation from a single 1.8-V supply. The measured eye-diagrams of the array confirm wide and clear eye-openings up to 1.3-Gb/s operations. Also, the optical pulse measurements estimate that the proposed 16-channel TIA array chip can detect signals within 20 meters away from the laser source. The whole chip occupies the area of $5.0{\times}1.1mm^2$ including I/O pads. For comparison, a current-mode 16-channel TIA array is also realized in the same $0.18-{\mu}m$ CMOS technology, which exploits regulated-cascode (RGC) input configuration. Measurements reveal that the I-TIA array achieves superior performance in optical pulse measurements.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.617-630
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• 1996

In this paper, a shared-concurrent file system (S-CFS) is designed and implemented using conventional disks as disk arrays on a Workstation Cluster which can be used as a small-scale server. Since it is implemented on UNIX operating systems, S_CFS is not only portable and flexible but also efficient in resource usage because it does not require additional I/O nodes. The result of the research shows that on small-scale systems with enough disks, the performance of the concurrent file system on transaction processing applications is bounded by the bottleneck of CPUs computing powers while the performance of the concurrent file system on massive data I/Os is bounded by the time required to copy data between buffers. The concurrent file system,which has been implemented on a Workstation Cluster with 8 disks,shows a throughput of 388 tps in case of transaction processing applications and can provide the bandwidth of 15.8 Mbytes/sec in case of massive data processing applications. Moreover,the concurrent file system has been dsigned to enhance the throughput of applications requirring high performance I/O by controlling the paralleism of the concurrent file system on user's side.

• Journal of Communications and Networks
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• v.8 no.1
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• pp.28-37
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• 2006

State-dependent call admission control (SDCAC) is proposed to make efficient use of scarce wireless resource in a hierarchical wireless network with heterogeneous traffic. With SDCAC, new calls are accepted according to an acceptance probability taking account of not only cell dwell time but also call holding time and system state (i.e., occupied bandwidth). An analytical method is developed to calculate performance measures of interest, e.g., new call blocking probability, forced termination probability, over. all weighted blocking probability. Numerical results with not only stationary but nonstationary traffic loads are presented to show the robustness of SDCAC. It is shown that SDCAC performs much better than the other considered schemes under nonstationary traffic load.