• Journal of Electrochemical Science and Technology
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• 제10권4호
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• pp.424-432
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• 2019

Planar BiVO₄ and 3 wt% Mo-doped BiVO₄ (abbreviated as Mo:BiVO₄) film were prepared by the facile spin-coating method on fluorine doped SnO₂(FTO) substrate in the same precursor solution including the Mo precursor in Mo:BiVO₄ film. After annealing at a high temperature of 450℃ for 30 min to improve crystallinity, the films exhibited the monoclinic crystalline phase and nanoporous architecture. Both films showed no remarkably discrepancy in crystalline or morphological properties. To investigate the effect of surface passivation exploring the Al₂O₃ layer, the ultra-thin Al₂O₃ layer with a thickness of approximately 2 nm was deposited on BiVO₄ film using the atomic layer deposition (ALD) method. No distinct morphological modification was observed for all prepared BiVO₄ and Mo:BiVO₄ films. Only slightly reduced nanopores were observed. Although both samples showed some reduction of light absorption in the visible wavelength after coating of Al₂O₃ layer, the Al₂O₃ coated BiVO₄ (Al₂O₃/BiVO₄) film exhibited enhanced photoelectrochemical performance in 0.5 M Na₂SO₄ solution (pH 6.5), having higher photocurrent density (0.91 mA/㎠ at 1.23 V vs. reversible hydrogen electrode (RHE), briefly abbreviated as V_RHE) than BiVO₄ film (0.12 mA/㎠ at 1.23 V_RHE). Moreover, Al₂O₃ coating on the Mo:BiVO₄ film exhibited more enhanced photocurrent density (1.5 mA/㎠ at 1.23 V_RHE) than the Mo:BiVO₄ film (0.86 mA/㎠ at 1.23 V_RHE). To examine the reasons, capacitance measurement and Mott-Schottky analysis were conducted, revealing that the significant degradation of capacitance value was observed in both BiVO₄ film and Al₂O₃/Mo:BiVO₄ film, probably due to degraded capacitance by surface passivation. Furthermore, the flat-band potential (V_FB) was negatively shifted to about 200 mV while the electronic conductivities were enhanced by Al₂O₃ coating in both samples, contributing to the advancement of PEC performance by ultra-thin Al₂O₃ layer.

• 한국광학회지
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• 제3권4호
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• pp.258-265
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• 1992

저압화학기상증착법으로 Si 기판에 $P_{2}O_{5}-SiO_{2}$ 광도파박막계를 제작하였다. 제작된 박막의 광도파손실율은 1.65dB/cm이었으나 $1100^{\circ}C$에서 열처리한 뒤에는 0.1dB/cm 이하로 크게 감소하였다. 레이저 노광법과 활성이온식각법으로 광도파로를 제작하여 $1100^{\circ}C$에서 열처리하였다. 열처리 결과 도파로 코어의 모양은 사각형에서 반원형으로 바뀌었으며 0.6328$\mu$m에서 0.03dB/cm 그리고 1.53$\mu$m에서 0.04dB/cm의 낮은 도파손실율을 나타내었다. 도파로의 도파손실율이 감소하는 이유로는 고온 열처리과정에서 첫째 박막조직과 결합하여 광흡수를 일으키는 수소가 확산 방출되고 둘째 광산란을 일으키는 도파로의 거친 계면 및 박막조직이 재형성되며, 셋째 식각법으로 도파로를 만들때 생기는 도파로 코어의 거친 계면이 매끄럽게되어 도파광의 산란손실이 중어들기 때문으로 생각된다.

• 전기전자학회논문지
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• 제20권3호
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• pp.220-225
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• 2016

본 논문은 전류 센싱 FET가 내장되어 있고 온-저항이 낮으며 고전류 구동이 가능한 트렌치 게이트 고 전력 MOSFET를 제안하고 전기적 특성을 분석하였다. 트렌치 게이트 전력 소자는 트렌치 폭 $0.6{\mu}m$, 셀 피치 $3.0{\mu}m$로 제작하였으며 내장된 전류 센싱 FET는 주 전력 MOSFET와 같은 구조이다. 트렌치 게이트 MOSFET의 집적도와 신뢰성을 향상시키기 위하여 자체 정렬 트렌치 식각 기술과 수소 어닐링 기술을 적용하였다. 또한, 문턱전압을 낮게 유지하고 게이트 산화막의 신뢰성을 증가시키기 위하여 열 산화막과 CVD 산화막을 결합한 적층 게이트 산화막 구조를 적용하였다. 실험결과 고밀도 트렌치 게이트 소자의 온-저항은 $24m{\Omega}$, 항복 전압은 100 V로 측정되었다. 측정한 전류 센싱 비율은 약 70 정도이며 게이트 전압변화에 대한 전류 센싱 변화율은 약 5.6 % 이하로 나타났다.

• Journal of Electrochemical Science and Technology
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• 제9권4호
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• pp.282-291
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• 2018

The pristine fluorine-doped $SnO_2$ (abbreviated as FTO) inverse opal (IO) was developed using a 410 nm polystyrene bead template. The nanolayered copper tungsten oxide ($CuWO_4$) was decorated on the FTO IO film using a facile electrochemical deposition, subsequently followed by annealing at $500^{\circ}C$ for 90 min. The morphologies, crystalline structure, optical properties and photoelectrochemical characteristics of the FTO and $CuWO_4$-decorated FTO (briefly denoted as $FTO/CuWO_4$) IO film were investigated by field emission scanning electron microscopy, X-ray diffraction, UV-vis spectroscopy and electrochemical impedance spectroscopy, showing FTO IO in the hexagonally closed-pack arrangement with a pore diameter and wall thickness of about 300 nm and 20 nm, respectively. Above this film, the $CuWO_4$ was electrodeposited by controlling the cycling number in cyclic voltammetry, suggesting that the $CuWO_4$ formed during 4 cycles (abbreviated as $CuWO_4$(4 cycles)) on FTO IO film exhibited partial distribution of $CuWO_4$ nanoparticles. Additional distribution of $CuWO_4$ nanoparticles was observed in the case of $FTO/CuWO_4$(8 cycles) IO film. The $CuWO_4$ layer exhibits triclinic structure with an indirect band gap of approximately 2.5 eV and shows the enhanced visible light absorption. The photoelectrochemical (PEC) behavior was evaluated in the 0.5 M $Na_2SO_4$ solution under solar illumination, suggesting that the $FTO/CuWO_4$(4 cycles) IO films exhibit a photocurrent density ($J_{sc}$) of $0.42mA/cm^2$ at 1.23 V vs. reversible hydrogen electrode (RHE, denoted as $V_{RHE}$), while the FTO IO and $FTO/CuWO_4$(8 cycles) IO films exhibited a $J_{sc}$ of 0.14 and $0.24mA/cm^2$ at $1.23V_{RHE}$, respectively. This difference can be explained by the increased visible light absorption by the $CuWO_4$ layer and the favorable charge separation/transfer event in the cascading band alignment between FTO and $CuWO_4$ layer, enhancing the overall PEC performance.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.107-108
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• 2008

The spectacular development of AMLCDs, been made possible by a-Si:H technology, still faces two major drawbacks due to the intrinsic structure of a-Si:H, namely a low mobility and most important a shift of the transfer characteristics of the TFTs when submitted to bias stress. This has lead to strong research in the crystallization of a-Si:H films by laser and furnace annealing to produce polycrystalline silicon TFTs. While these devices show improved mobility and stability, they suffer from uniformity over large areas and increased cost. In the last decade we have focused on microcrystalline silicon (${\mu}c$-Si:H) for bottom gate TFTs, which can hopefully meet all the requirements for mass production of large area AMOLED displays [1,2]. In this presentation we will focus on the transfer of a deposition process based on the use of $SiF_4$-Ar-$H_2$ mixtures from a small area research laboratory reactor into an industrial gen 1 AKT reactor. We will first discuss on the optimization of the process conditions leading to fully crystallized films without any amorphous incubation layer, suitable for bottom gate TFTS, as well as on the use of plasma diagnostics to increase the deposition rate up to 0.5 nm/s [3]. The use of silicon nanocrystals appears as an elegant way to circumvent the opposite requirements of a high deposition rate and a fully crystallized interface [4]. The optimized process conditions are transferred to large area substrates in an industrial environment, on which some process adjustment was required to reproduce the material properties achieved in the laboratory scale reactor. For optimized process conditions, the homogeneity of the optical and electronic properties of the ${\mu}c$-Si:H films deposited on $300{\times}400\;mm$ substrates was checked by a set of complementary techniques. Spectroscopic ellipsometry, Raman spectroscopy, dark conductivity, time resolved microwave conductivity and hydrogen evolution measurements allowed demonstrating an excellent homogeneity in the structure and transport properties of the films. On the basis of these results, optimized process conditions were applied to TFTs, for which both bottom gate and top gate structures were studied aiming to achieve characteristics suitable for driving AMOLED displays. Results on the homogeneity of the TFT characteristics over the large area substrates and stability will be presented, as well as their application as a backplane for an AMOLED display.