• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.368-376
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• 2006

This paper describes a Fcore_GenSim(Parameterized FFT Core Generation & Simulation Program), which can be used as an essential If(Intellectual Property) in various OFDM modem designs. The Fcore_Gensim is composed of two parts, a parameterized core generator(PFFT_CoreGen) that generates Verilog-HDL models of FFT cores, and a fixed-point FFT simulator(FXP_FFTSim) which can be used to estimate the SQNR performance of the generated cores. The parameters that can be specified for core generation are FFT length in the range of 64 ~2048-point and word-lengths of input/output/internal/twiddle data in the range of 8-b "24-b with 2-b step. Total 43,659 FFT cores can be generated by Fcore_Gensim. In addition, CBFP(Convergent Block Floating Point) scaling can be optionally specified. To achieve an optimized hardware and SQNR performance of the generated core, a hybrid structure of R2SDF and R2SDC stages and a hybrid algorithm of radix-2, radix-2/4, radix-2/4/8 are adopted according to FFT length and CBFP scaling.

• Journal of Advanced Navigation Technology
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• v.1 no.1
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• pp.23-34
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• 1997

A multi-channel digital GPS receiver has been developed including a RF-to-IF engine (engine 1), a digital signal processing engine (engine 2) with a microprocessor interfacing, and a navigation software. A high speed SiGe heterojunction bipolar transistor (HBT) as a active device has been mounted on chip-on-board (COB) type hybrid ICs such as LNA, mixer, and VCO in RF front-end of the engine 1 board. A 6-channel digital correlator together with a real-time clock and a microprocessor interface has been realized using an Altera Flex 10K FPGA as well as ASIC technology. Navigation software controlling the correlator for GPS signal tracking, retrieval and storing a message retrieval, and position calculation has been implemented. The GPS receiver was tested using a single channel STR2770 simulator. Successful navigation message retrieval and position determination was confirmed.

• Journal of KIISE
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• v.42 no.3
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• pp.379-389
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• 2015

With the advent of non-volatile memories such as Phase Change Memory (PCM or PRAM) and Magneto Resistive RAM (MRAM), active studies have been carried out on how to replace Dynamic Random-Access Memory (DRAM) with PRAM. In this paper, we study both endurance and performance issues of existing join algorithms that are based on PRAM-based computer systems and have been widely used until now: Block Nested Loop Join, Sort-Merge Join, Grace Hash Join, and Hybrid Hash Join. Our experimental results show that the existing join algorithms need to be redesigned to improve both the endurance and performance of PRAMs. To the best of our knowledge, this is the first research to scientifically study the results of the four join algorithms running on PRAM-based systems. In this work, our main contribution is the modeling and implementation of a PRAM-based simulator for a comparative study of the existing join algorithms.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.6
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• pp.2269-2275
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• 2010

The performance of Genetic Algorithms (GA) is affected by various factors such as parameters, genetic operators and strategies. The traditional approach with random initial population is efficient however the whole initial population may contain many infeasible solutions. Thus it would take a long time for GA to produce a good solution. The GA have been modified in various ways to achieve faster convergence and it was particularly recognized by researchers that initial population greatly affects the performance of GA. This study proposes modified GA with sorted initial population and applies it to solving Travelling Salesman Problem (TSP). Normally, the bigger the initial the population is the more computationally expensive the calculation becomes with each generation. New approach allows reducing the size of the initial problem and thus achieve faster convergence. The proposed approach is tested on a simulator built using object-oriented approach and the test results prove the validity of the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11A
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• pp.1106-1112
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• 2007

As a demand for high speed uplink packet services increases, the WCDMA enhanced uplink, also known as high speed uplink packet access (HSUPA), has been specified in release 6 by 3GPP. This HSUPA will provide various types of multimedia services, such as real-time video streaming, gaming, VoIP, and FTP. Generally, the performance of HSUPA is dominated by scheduling policy. Therefore, it is required to design a scheduling algorithm considering the traffic characteristics to provide QoS guaranteed services in various traffic environments. In this paper, we propose a scheduling algorithm considering the traffic characteristics to guarantee QoS in a mixed traffic environment. Finally, the performance of the proposed scheduling algorithm is evaluated in terms of average packet delay, packet delay jitter, and system throughput using a system level simulator.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.8
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• pp.1605-1614
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• 2009

The technique of simultaneous localization and mapping is the most important research topic in mobile robotics. In the process of building a map in its available memory, the robot memorizes environmental information on the plane of grid or topology. Several approaches about this technique have been presented so far, but most of them use mapping technique as either grid-based map or topology-based map. In this paper we propose a frame of solving the SLAM problem of linking map covering, map building, localizing, path finding and obstacle avoiding in an automatic way. Some algorithms integrating grid and topology map are considered and this make the SLAM performance faster and more stable. The proposed scheme uses an occupancy grid map in representing the environment and then formulate topological information in path finding by A${\ast}$ algorithm. The mapping process is shown and the shortest path is decided on grid based map. Then topological information such as direction, distance is calculated on simulator program then transmitted to robot hardware devices. The localization process and the dynamic obstacle avoidance can be accomplished by topological information on grid map. While mapping and moving, pose of the robot is adjusted for correct localization by implementing additional pixel based image layer and tracking some features. A laser range finer and electronic compass systems are implemented on the mobile robot and DC geared motor wheels are individually controlled by the adaptive PD control method. Simulations and experimental results show its performance and efficiency of the proposed scheme are increased.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.719-728
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• 2015

This paper presents the results of field tests on Voltage Management System (VMS) using hybrid voltage control, which utilizes coordinated controls of various reactive power resources such as generators, FACTS and switched shunt devices to regulate the pilot bus voltage in a voltage control area. It also includes the results of performance test on RTDS-based test bed in order to validate the VMS before installing it in Jeju power system. The main purpose of the system is adequately to regulate the reactive power reserve of key generators in a normal condition with coordination of discrete shunt devices such as condensers and reactors so that the reserves can avoid voltage collapse in emergency state in Jeju system. Field tests in the automatic mode of VMS operation are included in steady-states and transient states. Finally, by the successful operation of VMS in Jeju power system, the VMS is proved to effectively control system voltage profiles in steady-state condition, increase system MVAR reserves and improve system reliability for pre- and post-contingency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.7B
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• pp.477-487
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• 2008

Congestion control of the TCP reduces transmission rate when it detects packet loss because packet loss origines from congestion in the wired network. In the wireless network, packet loss comes from channel errors. Wired TCP degrades performance when there are wireless losses because it does not classify type of loss. These day, there are many researches which classify type of loss between congestion loss and wireless loss for wired-wireless hybrid network. For wireless TCP, many of existing algorithms are based on the estimated bandwidth or variations of packet arrival time. In this paper, we propose a new TCP scheme to distinguish the wireless packet losses from the congestion packet losses using MIB of the IEEE 802.11 MAC. We perform excessive simulations using the NS-2 network simulator and analyze the simulation results to compare the performance of the proposed algorithm to other well-known algorithms. From simulation results, we know that proposed algorithm improves performance about 12% and 32% compared with Spike algorithm and mBiaz algorithm, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6B
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• pp.456-468
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• 2008

In this paper, we design Input/Output modules as a preference work for implementation of hybrid two stage AWG based WDM-PON and verify operations of each function modules through the logic simulation. This WDM-PON system provides service to 128 ONUs through 32 wavelength and one wavelength is shared for upstream transmission with four ONU while each wavelength is allocated to each ONU for downstream transmission. The designed WDM-PON MAC chip is based on sub-MAC which consists of one control unit and reception unit and four transmission unit. To design the reception and transmission unit of sub-MAC, we define the functions of the sub-MAC, pins of the modules, control signal and timing of each signal. We intend to design MAC chip with 1Gbps transmission rate. Thus the designed MAC chip is worked on 125MHz clock rate. We define FSM and design Input/Output modules with VHDL. The logic simulation of the modules is executed by the ModelSIM simulator.

• Journal of the Korea Society of Computer and Information
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• v.17 no.12
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• pp.11-22
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• 2012

This paper proposes for practical engineers a lightweight modeling and simulation environment for continuous system models specified in ordinary differential equations, which are time-domain specification of such systems. We propose a block-oriented specification formalism that has two levels: one for atomic behavior and the other the structure of models. Also we provide with a simulation framework, called BlockSim++, which make models specified in the block-oriented formalism be easily translated in object-oriented program that runs with the proposed simulation framework. The proposed formalism and framework has advantage of reuse such that it can be easily integrated into application programs and heterogeneous simulators. We illustrates the usefulness of the proposed framework by a simple hybrid modeling simulation example.