• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.65-70
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• 2024

Direct cache-to-cache transfer has been studied to reduce the latency and bandwidth consumption related to the shared data in multiprocessor system. Even though these studies lead to meaningful results, they assume that caches consist of SRAM. For example, if the system employs the non-volatile memory, the one of the most important parts to consider is to decrease the number of write operations. This paper proposes a hybrid write avoidance cache coherence protocol that considers the hybrid cache architecture. A new state is added to finely control what is stored in the non-volatile memory area, and experimental results showed that the number of writes was reduced by about 36% compared to the existing schemes.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.193-204
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• 2017

Various 3D-stacked DRAMs have been proposed to overcome the memory wall problem. Hybrid Memory Cube (HMC) is a true 3D-stacked DRAM with stacked DRAM layers on top of a logic layer. The logic die is mainly used to implement a memory controller for HMC, and it is connected through a high speed serial link called SerDes with a host that is either a processor or another HMC. In HMC, the serial link is crucial for both performance and power consumption. Therefore, it is important that the link is configured properly so that the required performance should be satisfied while the power consumption is minimized. In this paper, we propose a HMC system model included the high speed serial link to estimate performance accurately. Since the link modeling strictly follows the link flow control mechanism defined in the HMC spec, the actual HMC performance can be estimated accurately with respect to each link configuration. Various simulations are conducted in order to deduce the correlation between the HMC performance and the link configuration with regard to memory utilization. It is confirmed that there is a strong correlation between the achievable maximum performance of HMC and the link configuration in terms of both bandwidth and latency. Therefore, it is possible to find the best link configuration when the required HMC performance is known in advance, and finding the best configuration will lead to significant power saving while the performance requirement is satisfied.

• Smart Structures and Systems
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• v.19 no.4
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• pp.341-350
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• 2017

Based on the super elastic properties of the shape memory alloy (SMA) and the inverse piezoelectric effect of piezoelectric (PZT) ceramics, a kind of hybrid semi-active control device was designed and made, its mechanical properties test was done under different frequency and different voltage. The local search ability of genetic algorithm is poor, which would fall into the defect of prematurity easily. A kind of adaptive immune memory cloning algorithm(AIMCA) was proposed based on the simulation of clone selection and immune memory process. It can adjust the mutation probability and clone scale adaptively through the way of introducing memory cell and antibody incentive degrees. And performance indicator based on the modal controllable degree was taken as antigen-antibody affinity function, the optimization analysis of damper layout in a space truss structure was done. The structural seismic response was analyzed by applying the neural network prediction model and T-S fuzzy logic. Results show that SMA and PZT friction composite damper has a good energy dissipation capacity and stable performance, the bigger voltage, the better energy dissipation ability. Compared with genetic algorithm, the adaptive immune memory clone algorithm overcomes the problem of prematurity effectively. Besides, it has stronger global searching ability, better population diversity and faster convergence speed, makes the damper has a better arrangement position in structural dampers optimization leading to the better damping effect.

• Journal of KIISE
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• v.42 no.11
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• pp.1314-1321
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• 2015

Mobile devices employ buffer cache mechanisms, just as in computer systems such as desktops or servers, to mitigate the performance gap between main memory and secondary storage. However, DRAM has a problem in that it accelerates battery consumption by performing refresh operations periodically to maintain the stored data. In this paper, we propose a novel buffer cache scheme to increase the battery lifecycle in mobile devices based on a hybrid main memory architecture consisting of DRAM and non-volatile PCM. We also suggest a new buffer cache policy that allocates buffers based on process states to optimize the performance and endurance of PCM. In particular, our algorithm allocates each page to the appropriate position corresponding to the state of the application that owns the page, and tries to ensure a rapid response of foreground applications even with a small amount of DRAM memory. The experimental results indicate that the proposed scheme reduces the elapsed time of foreground applications by 58% on average and power consumption by 23% on average without negatively impacting the performance of background applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.3
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• pp.135-140
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• 2016

In this study, we developed the solution-processed PMMA-$HfO_x$ hybrid ReRAM devices to overcome the respective drawbacks of organic and inorganic materials. The performances of PMMA-$HfO_x$ hybrid ReRAM were compared to those of PMMA- and $HfO_x$-based ReRAMs. Bipolar resistive switching behavior was observed from these ReRAMs. The PMMA-$HfO_x$ hybrid ReRAMs showed a larger operation voltage margin and memory window than PMMA-based and $HfO_x$-based ReRAMs. The reliability and electrical instability of ReRAMs were remarkably improved by blending the $HfO_x$ into PMMA. An Ohmic conduction path was commonly generated in the LRS (low resistance state). In HRS (high resistance state), the PMMA-based ReRAM showed SCLC (space charge limited conduction). the PMMA-$HfO_x$ hybrid ReRAM and $HfO_x$-based ReRAM revealed the Pool-Frenkel conduction. As a result of flexibility test, serious defects were generated in $HfO_x$ film deposited on PI (polyimide) substrate. On the other hand, the PMMA and PMMA-$HfO_x$ films showed an excellent flexibility without defect generation.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.39 no.2
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• pp.191-197
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• 2015

The message passing interface (MPI) and hybrid programming models for the parallel computation of a pressure equation were compared in a distributed memory system. Both models were based on domain decomposition, and two numbers of the sub-domain were selected by considering the efficiency of the hybrid model. The parallel performances for various problem sizes were measured using up to 96 threads. It was found that in addition to the cache-memory size, the overhead of the MPI communication/OpenMP directives affected the parallel performance. For small problems, the parallel performance was low because the percentage of the overhead of the MPI communication/OpenMP directives increased as the number of threads increased, and MPI was better than the hybrid model because it had a smaller communication overhead. For large problems, the parallel performance was high because, in addition to the cache effect, the percentage of the communication overhead was relatively low compared to that for small problems, and the hybrid model was better than MPI because the communication overhead of MPI was more dominant than that of the OpenMP directives in the hybrid model.

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.1
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• pp.90-94
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• 2020

Artificial intelligence (AI) is software that learns large amounts of data and provides the desired results for certain patterns. In other words, learning a large amount of data is very important, and the role of memory in terms of computing systems is important. Massive data means wider bandwidth, and the design of the memory system that can provide it becomes even more important. Providing wide bandwidth in AI systems is also related to power consumption. AlphaGo, for example, consumes 170 kW of power using 1202 CPUs and 176 GPUs. Since more than 50% of the consumption of memory is usually used by system chips, a lot of investment is being made in memory technology for AI chips. MRAM, PRAM, ReRAM and Hybrid RAM are mainly studied. This study presents various memory technologies that are being studied in artificial intelligence chip design. Especially, MRAM and PRAM are commerciallized for the next generation memory. They have two significant advantages that are ultra low power consumption and nearly zero leakage power. This paper describes a comparative analysis of the four representative new memory technologies.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.135-140
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• 2020

Recently, due to the rapid diffusion of intelligent systems and IoT technologies, power saving techniques in real-time embedded systems has become important. In this paper, we propose P-GA (Parallel Genetic Algorithm), a scheduling algorithm aims at reducing the power consumption of real-time systems in multi-core hybrid memory environments. P-GA improves the Proportional-Fairness (PF) algorithm devised for multi-core environments by combining the dynamic voltage/frequency scaling of the processor with the nonvolatile memory technologies. Specifically, P-GA applies genetic algorithms for optimizing the voltage and frequency modes of processors and the memory types, thereby minimizing the power consumptions of the task set. Simulation experiments show that the power consumption of P-GA is reduced by 2.85 times compared to the conventional schemes.

• Journal of KIISE:Software and Applications
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• v.31 no.3
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• pp.369-378
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• 2004

In partially free word order languages like Korean and Japanese, the rule-based method is effective for text chunking, and shows the performance as high as machine learning methods even with a few rules due to the well-developed overt Postpositions and endings. However, it has no ability to handle the exceptions of the rules. Exception handling is an important work in natural language processing, and the exceptions can be efficiently processed in memory-based teaming. In this paper, we propose a hybrid of rule-based method and memory-based learning for Korean text chunking. The proposed method is primarily based on the rules, and then the chunks estimated by the rules are verified by memory-based classifier. An evaluation of the proposed method on Korean STEP 2000 corpus yields the improvement in F-score over the rules or various machine teaming methods alone. The final F-score is 94.19, while those of the rules and SVMs, the best machine learning method for this task, are just 91.87 and 92.54 respectively.

• Composites Research
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• v.17 no.4
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• pp.18-24
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• 2004

In this paper, active shape control of composite structures actuated by shape memory alloy (SMA) wires is presented. The thermo-mechanical behaviors of SMA wires were experimentally measured. Hybrid composite structures were established by attaching SMA actuators on the surfaces of graphite/epoxy composite beams using bolt-joint connectors. SMA actuators were activated by phase transformation, which induced by temperature rising over austenite finish temperature. In this paper, electrical resistive heating was applied to the hybrid composite structures to activate the SMA actuators. For (aster and more accurate shape/deflection control of the hybrid composite structure, PID feedback controller was designed from numerical simulations and experimentally applied to the SMA actuators.