• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.343-346
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• 2002

This paper presents a Prototype system developed for a Bluetooth interfaced VoIP system. The VoIP phone is developed based on tile implementation of a CELP coder on the TI 16bit DSP Processor A PC interfaced with Bluetooth module is used to designing a access point system. Host controller protocol stack is implemented to realize gateway between the wireless and wired line networks. A server application program for user management and call processing, which is based on TCP/IP peer to peer connection, is implemented for tile evaluation of overall interface system.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.709-712
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• 2003

In this research, we port the RT-Linux to MVME 5100 board which is driven by VxWorks or Vertex until now. And, we developed the data logging modules by using the RT-Linux. This module gathers two different scan timing data from plant and sends this data to the host controller with real time.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.628-632
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• 2003

An intelligent miniature humanoid robot system is designed and implemented as a platform for researching walking algorithm. The robot system consists of a mechanical robot body, a control system, a sensor system, and a human interface system. The robot has 6 dofs per leg, 3 dofs per arm, and 2 dofs for a neck, so it has total of 20 dofs to have dexterous motion capability. For the control system, a supervisory controller runs on a remote host computer to plan high level robot actions based on the vision sensor data, a main controller implemented with a DSP chip generates walking trajectories for the robot to perform the commanded action, and an auxiliary controller implemented with an FPGA chip controls 20 actuators. The robot has three types of sensors. A two-axis acceleration sensor and eight force sensing resistors for acquiring information on walking status of the robot, and a color CCD camera for acquiring information on the surroundings. As an example of an intelligent robot action, some experiments on playing soccer are performed.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.595-602
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• 1994

PERISTOR-3000 loaded with 32 bit DSP(Digital Signal Processor) is a technically advanced versatile dc motor controller in applications with very high requirements for rapid response, control accuracy and reliability. The current controller of PERISTOR-3000 is of the predictive type and gives fast control with both discontinuous and continuous current compared to the conventional PI current control. The speed controller gain is compensated to improve response behavior. PERISTOR-3000 communicates with its host computer, POSTAR-3200, or any IBM or compatible PC and can be controlled. Dedicated monitoring system for MMI is introduced.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.5
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• pp.263-272
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• 2011

The complexity of flash memory based storage systems is high due to diverse host interfaces and other design choices such as mapping granularity, flash memory controller execution models and so on. Thus, it is possible that the actual performance after implementation is not consistent with the target performance. This paper demonstrates that the performance prediction of flash memory based storage systems is possible through performance modeling that takes into account various design parameters. In the performance modeling, the FTL, which is the core element of flash memory based storage systems, is modeled as a set of (copy-on-write) logs and their interactions. Also, the flash memory controller is modeled based on the classification proposed in the design of the Ozone flash controller. In this study, the performance model has been implemented using Simulink and experimental results are presented and analyzed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.369-378
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• 2003

This paper presents design and VLSI implementations of a reassembly processor for ATM/AAL. The assembly processor is responsible for processing ATM cells from the receive physical interface. It controls the transfer of the AAL payload to host memory and performs all necessary SAR and CPCS checks. We propose the improved structure of cell identification algorithm and smart scatter method for host memory management. The proposed cell identification algorithm quickly locates the appropriate reassembly VC table based on the received VPI./VCI channel value in the ATM header. The cell identification algorithm also allow complete freedom in assignment of VCI/VPI values. The reassembly processor uses a smart scatter method to write cell payload data to host memory. It maintains the scatter operation and controls the incoming DMA block during scatter DMA to host memory. The proposed reassembly processor can perform reassembly checks on AAL. OAM cell. For an AAL5 connection, only CPCS checks, including the CRC32, are performed. In this paper, we proposed a practical reassembly architecture. The design of reassembly processor has become feasible using 0.6${\mu}{\textrm}{m}$ CMOS gate array technology.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.320-324
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• 2003

Recently, Virtual reality parts is applied in various fields of industry. In this paper we got under control motion of reality robot from interface manipulation in the virtual world. This paper created virtual robot using of 3D Graphic Tool. And we reappeared a similar image with reality robot put on texture the use of components of Direct 3D Graphic. Also a reality robot and a virtual robot is controlled by joystick. The developed robot consists of robot controller with vision system and host PC program. The robot and camera can move with 2 degree of freedom by independent remote controlling a user friendly designed joystick. An environment is recognized by the vision system and ultra sonic sensors. The visual mage and command data translated through 900MHz and 447MHz RF controller, respectively. If user send robot control command the use of simulator to control the reality robot, the transmitter/recever got under control until 500miter outdoor at the rate of 4800bps a second in Hlaf Duplex method via radio frequency module useing 447MHz frequency.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.2
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• pp.124-129
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• 2013

Hexapod walking robots are superior to biped or quadruped ones in terms of walking stability. Therefore hexapod robots have the advantage in performing intelligent tasks based on walking stability. In this paper, we propose a hexapod robot that has one fore leg, one hind leg, two left legs, and two right legs and can perform various intelligent tasks. We build the robot by using 26 motors and implement a controller which consists of a host PC, a DSP main controller, an AVR auxiliary controller, and smart phone/pad. We show by several experiments that the implemented robot can perform various intelligent tasks such as uneven surface walking, tracking and kicking a ball, remote control and 3D monitoring by using data obtained from stereo camera, infrared sensors, ultra sound sensors, and contact sensors.

• KIISE Transactions on Computing Practices
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• v.23 no.8
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• pp.473-480
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• 2017

In recent years, semiconductor-based storage devices such as flash memory (SSDs) have been developed to high performance. In addition, a trend has been observed of optimally utilizing resources such as the central processing unit (CPU) and memory of the internal controller in the storage device according to the needs of the application. This concept is called In-Storage Processing (ISP). In a storage device equipped with the ISP function, it is possible to process part of the operation executed on the host system, thus reducing the load on the host. Moreover, since the data is processed in the storage device, the data transferred to the host are reduced. In this paper, we propose a method to optimize graph query processing by utilizing these ISP functions, and show that the optimized graph processing method improves the performance of the graph 500 benchmark by up to 20%.